SameBoy | Accurate GB/GBC emulator |
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BootROMs/hardware.inc
1 ;*
2 ;* Gameboy Hardware definitions
3 ;* https://github.com/gbdev/hardware.inc
4 ;*
5 ;* Based on Jones' hardware.inc
6 ;* And based on Carsten Sorensen's ideas.
7 ;*
8 ;* To the extent possible under law, the authors of this work have
9 ;* waived all copyright and related or neighboring rights to the work.
10 ;* See https://creativecommons.org/publicdomain/zero/1.0/ for details.
11 ;*
12 ;* SPDX-License-Identifier: CC0-1.0
13 ;*
14 ;* Rev 1.1 - 15-Jul-97 : Added define check
15 ;* Rev 1.2 - 18-Jul-97 : Added revision check macro
16 ;* Rev 1.3 - 19-Jul-97 : Modified for RGBASM V1.05
17 ;* Rev 1.4 - 27-Jul-97 : Modified for new subroutine prefixes
18 ;* Rev 1.5 - 15-Aug-97 : Added _HRAM, PAD, CART defines
19 ;* : and Nintendo Logo
20 ;* Rev 1.6 - 30-Nov-97 : Added rDIV, rTIMA, rTMA, & rTAC
21 ;* Rev 1.7 - 31-Jan-98 : Added _SCRN0, _SCRN1
22 ;* Rev 1.8 - 15-Feb-98 : Added rSB, rSC
23 ;* Rev 1.9 - 16-Feb-98 : Converted I/O registers to $FFXX format
24 ;* Rev 2.0 - : Added GBC registers
25 ;* Rev 2.1 - : Added MBC5 & cart RAM enable/disable defines
26 ;* Rev 2.2 - : Fixed NR42,NR43, & NR44 equates
27 ;* Rev 2.3 - : Fixed incorrect _HRAM equate
28 ;* Rev 2.4 - 27-Apr-13 : Added some cart defines (AntonioND)
29 ;* Rev 2.5 - 03-May-15 : Fixed format (AntonioND)
30 ;* Rev 2.6 - 09-Apr-16 : Added GBC OAM and cart defines (AntonioND)
31 ;* Rev 2.7 - 19-Jan-19 : Added rPCMXX (ISSOtm)
32 ;* Rev 2.8 - 03-Feb-19 : Added audio registers flags (Álvaro Cuesta)
33 ;* Rev 2.9 - 28-Feb-20 : Added utility rP1 constants
34 ;* Rev 3.0 - 27-Aug-20 : Register ordering, byte-based sizes, OAM additions, general cleanup (Blitter Object)
35 ;* Rev 4.0 - 03-May-21 : Updated to use RGBDS 0.5.0 syntax, changed IEF_LCDC to IEF_STAT (Eievui)
36 ;* Rev 4.1 - 16-Aug-21 : Added more flags, bit number defines, and offset constants for OAM and window positions (rondnelson99)
37 ;* Rev 4.2 - 04-Sep-21 : Added CH3- and CH4-specific audio registers flags (ISSOtm)
38 ;* Rev 4.3 - 07-Nov-21 : Deprecate VRAM address constants (Eievui)
39 ;* Rev 4.4 - 11-Jan-22 : Deprecate VRAM CART_SRAM_2KB constant (avivace)
40 ;* Rev 4.5 - 03-Mar-22 : Added bit number definitions for OCPS, BCPS and LCDC (sukus)
41 ;* Rev 4.6 - 15-Jun-22 : Added MBC3 registers and special values
42 ;* Rev 4.7.0 - 27-Jun-22 : Added alternate names for some constants
43 ;* Rev 4.7.1 - 05-Jul-22 : Added RPB_LED_ON constant
44 ;* Rev 4.8.0 - 25-Oct-22 : Changed background addressing constants (zlago)
45 ;* Rev 4.8.1 - 29-Apr-23 : Added rOPRI (rbong)
46 ;* Rev 4.9.0 - 24-Jun-23 : Added definitions for interrupt vectors (sukus)
47 ;* Rev 4.9.1 - 11-Sep-23 : Added repository link and CC0 waiver notice
48
49
50 ; NOTE: REVISION NUMBER CHANGES MUST BE REFLECTED
51 ; IN `rev_Check_hardware_inc` BELOW!
52
53 IF __RGBDS_MAJOR__ == 0 && __RGBDS_MINOR__ < 5
54 FAIL "This version of 'hardware.inc' requires RGBDS version 0.5.0 or later."
55 ENDC
56
57 ; If all of these are already defined, don't do it again.
58
59 IF !DEF(HARDWARE_INC)
60 DEF HARDWARE_INC EQU 1
61
62 ; Usage: rev_Check_hardware_inc <min_ver>
63 ; Examples: rev_Check_hardware_inc 4.1.2
64 ; rev_Check_hardware_inc 4.1 (equivalent to 4.1.0)
65 ; rev_Check_hardware_inc 4 (equivalent to 4.0.0)
66 MACRO rev_Check_hardware_inc
67 DEF CUR_VER equs "4,9,1" ; ** UPDATE THIS LINE WHEN CHANGING THE REVISION NUMBER **
68
69 DEF MIN_VER equs STRRPL("\1", ".", ",")
70 DEF INTERNAL_CHK equs """MACRO ___internal
71 IF \\1 != \\4 || \\2 < \\5 || (\\2 == \\5 && \\3 < \\6)
72 FAIL "Version \\1.\\2.\\3 of 'hardware.inc' is incompatible with requested version \\4.\\5.\\6"
73 ENDC
74 \nENDM"""
75 INTERNAL_CHK
76 ___internal {CUR_VER}, {MIN_VER},0,0
77 PURGE CUR_VER, MIN_VER, INTERNAL_CHK, ___internal
78 ENDM
79
80
81 ;***************************************************************************
82 ;*
83 ;* General memory region constants
84 ;*
85 ;***************************************************************************
86
87 DEF _VRAM EQU $8000 ; $8000->$9FFF
88 DEF _SCRN0 EQU $9800 ; $9800->$9BFF
89 DEF _SCRN1 EQU $9C00 ; $9C00->$9FFF
90 DEF _SRAM EQU $A000 ; $A000->$BFFF
91 DEF _RAM EQU $C000 ; $C000->$CFFF / $C000->$DFFF
92 DEF _RAMBANK EQU $D000 ; $D000->$DFFF
93 DEF _OAMRAM EQU $FE00 ; $FE00->$FE9F
94 DEF _IO EQU $FF00 ; $FF00->$FF7F,$FFFF
95 DEF _AUD3WAVERAM EQU $FF30 ; $FF30->$FF3F
96 DEF _HRAM EQU $FF80 ; $FF80->$FFFE
97
98
99 ;***************************************************************************
100 ;*
101 ;* MBC registers
102 ;*
103 ;***************************************************************************
104
105 ; *** Common ***
106
107 ; --
108 ; -- RAMG ($0000-$1FFF)
109 ; -- Controls whether access to SRAM (and the MBC3 RTC registers) is allowed (W)
110 ; --
111 DEF rRAMG EQU $0000
112
113 DEF CART_SRAM_ENABLE EQU $0A
114 DEF CART_SRAM_DISABLE EQU $00
115
116
117 ; --
118 ; -- ROMB0 ($2000-$3FFF)
119 ; -- Selects which ROM bank is mapped to the ROMX space ($4000-$7FFF) (W)
120 ; --
121 ; -- The range of accepted values, as well as the behavior of writing $00,
122 ; -- varies depending on the MBC.
123 ; --
124 DEF rROMB0 EQU $2000
125
126 ; --
127 ; -- RAMB ($4000-$5FFF)
128 ; -- Selects which SRAM bank is mapped to the SRAM space ($A000-$BFFF) (W)
129 ; --
130 ; -- The range of accepted values varies depending on the cartridge configuration.
131 ; --
132 DEF rRAMB EQU $4000
133
134
135 ; *** MBC3-specific registers ***
136
137 ; Write one of these to rRAMG to map the corresponding RTC register to all SRAM space
138 DEF RTC_S EQU $08 ; Seconds (0-59)
139 DEF RTC_M EQU $09 ; Minutes (0-59)
140 DEF RTC_H EQU $0A ; Hours (0-23)
141 DEF RTC_DL EQU $0B ; Lower 8 bits of Day Counter ($00-$FF)
142 DEF RTC_DH EQU $0C ; Bit 7 - Day Counter Carry Bit (1=Counter Overflow)
143 ; Bit 6 - Halt (0=Active, 1=Stop Timer)
144 ; Bit 0 - Most significant bit of Day Counter (Bit 8)
145
146
147 ; --
148 ; -- RTCLATCH ($6000-$7FFF)
149 ; -- Write $00 then $01 to latch the current time into the RTC registers (W)
150 ; --
151 DEF rRTCLATCH EQU $6000
152
153
154 ; *** MBC5-specific register ***
155
156 ; --
157 ; -- ROMB1 ($3000-$3FFF)
158 ; -- A 9th bit that "extends" ROMB0 if more than 256 banks are present (W)
159 ; --
160 ; -- Also note that rROMB0 thus only spans $2000-$2FFF.
161 ; --
162 DEF rROMB1 EQU $3000
163
164
165 ; Bit 3 of RAMB enables the rumble motor (if any)
166 DEF CART_RUMBLE_ON EQU 1 << 3
167
168
169 ;***************************************************************************
170 ;*
171 ;* Memory-mapped registers
172 ;*
173 ;***************************************************************************
174
175 ; --
176 ; -- P1 ($FF00)
177 ; -- Register for reading joy pad info. (R/W)
178 ; --
179 DEF rP1 EQU $FF00
180
181 DEF P1F_5 EQU %00100000 ; P15 out port, set to 0 to get buttons
182 DEF P1F_4 EQU %00010000 ; P14 out port, set to 0 to get dpad
183 DEF P1F_3 EQU %00001000 ; P13 in port
184 DEF P1F_2 EQU %00000100 ; P12 in port
185 DEF P1F_1 EQU %00000010 ; P11 in port
186 DEF P1F_0 EQU %00000001 ; P10 in port
187
188 DEF P1F_GET_DPAD EQU P1F_5
189 DEF P1F_GET_BTN EQU P1F_4
190 DEF P1F_GET_NONE EQU P1F_4 | P1F_5
191
192
193 ; --
194 ; -- SB ($FF01)
195 ; -- Serial Transfer Data (R/W)
196 ; --
197 DEF rSB EQU $FF01
198
199
200 ; --
201 ; -- SC ($FF02)
202 ; -- Serial I/O Control (R/W)
203 ; --
204 DEF rSC EQU $FF02
205
206 DEF SCF_START EQU %10000000 ; Transfer Start Flag (1=Transfer in progress, or requested)
207 DEF SCF_SPEED EQU %00000010 ; Clock Speed (0=Normal, 1=Fast) ** CGB Mode Only **
208 DEF SCF_SOURCE EQU %00000001 ; Shift Clock (0=External Clock, 1=Internal Clock)
209
210 DEF SCB_START EQU 7
211 DEF SCB_SPEED EQU 1
212 DEF SCB_SOURCE EQU 0
213
214 ; --
215 ; -- DIV ($FF04)
216 ; -- Divider register (R/W)
217 ; --
218 DEF rDIV EQU $FF04
219
220
221 ; --
222 ; -- TIMA ($FF05)
223 ; -- Timer counter (R/W)
224 ; --
225 DEF rTIMA EQU $FF05
226
227
228 ; --
229 ; -- TMA ($FF06)
230 ; -- Timer modulo (R/W)
231 ; --
232 DEF rTMA EQU $FF06
233
234
235 ; --
236 ; -- TAC ($FF07)
237 ; -- Timer control (R/W)
238 ; --
239 DEF rTAC EQU $FF07
240
241 DEF TACF_START EQU %00000100
242 DEF TACF_STOP EQU %00000000
243 DEF TACF_4KHZ EQU %00000000
244 DEF TACF_16KHZ EQU %00000011
245 DEF TACF_65KHZ EQU %00000010
246 DEF TACF_262KHZ EQU %00000001
247
248 DEF TACB_START EQU 2
249
250
251 ; --
252 ; -- IF ($FF0F)
253 ; -- Interrupt Flag (R/W)
254 ; --
255 DEF rIF EQU $FF0F
256
257
258 ; --
259 ; -- AUD1SWEEP/NR10 ($FF10)
260 ; -- Sweep register (R/W)
261 ; --
262 ; -- Bit 6-4 - Sweep Time
263 ; -- Bit 3 - Sweep Increase/Decrease
264 ; -- 0: Addition (frequency increases???)
265 ; -- 1: Subtraction (frequency increases???)
266 ; -- Bit 2-0 - Number of sweep shift (# 0-7)
267 ; -- Sweep Time: (n*7.8ms)
268 ; --
269 DEF rNR10 EQU $FF10
270 DEF rAUD1SWEEP EQU rNR10
271
272 DEF AUD1SWEEP_UP EQU %00000000
273 DEF AUD1SWEEP_DOWN EQU %00001000
274
275
276 ; --
277 ; -- AUD1LEN/NR11 ($FF11)
278 ; -- Sound length/Wave pattern duty (R/W)
279 ; --
280 ; -- Bit 7-6 - Wave Pattern Duty (00:12.5% 01:25% 10:50% 11:75%)
281 ; -- Bit 5-0 - Sound length data (# 0-63)
282 ; --
283 DEF rNR11 EQU $FF11
284 DEF rAUD1LEN EQU rNR11
285
286
287 ; --
288 ; -- AUD1ENV/NR12 ($FF12)
289 ; -- Envelope (R/W)
290 ; --
291 ; -- Bit 7-4 - Initial value of envelope
292 ; -- Bit 3 - Envelope UP/DOWN
293 ; -- 0: Decrease
294 ; -- 1: Range of increase
295 ; -- Bit 2-0 - Number of envelope sweep (# 0-7)
296 ; --
297 DEF rNR12 EQU $FF12
298 DEF rAUD1ENV EQU rNR12
299
300
301 ; --
302 ; -- AUD1LOW/NR13 ($FF13)
303 ; -- Frequency low byte (W)
304 ; --
305 DEF rNR13 EQU $FF13
306 DEF rAUD1LOW EQU rNR13
307
308
309 ; --
310 ; -- AUD1HIGH/NR14 ($FF14)
311 ; -- Frequency high byte (W)
312 ; --
313 ; -- Bit 7 - Initial (when set, sound restarts)
314 ; -- Bit 6 - Counter/consecutive selection
315 ; -- Bit 2-0 - Frequency's higher 3 bits
316 ; --
317 DEF rNR14 EQU $FF14
318 DEF rAUD1HIGH EQU rNR14
319
320
321 ; --
322 ; -- AUD2LEN/NR21 ($FF16)
323 ; -- Sound Length; Wave Pattern Duty (R/W)
324 ; --
325 ; -- see AUD1LEN for info
326 ; --
327 DEF rNR21 EQU $FF16
328 DEF rAUD2LEN EQU rNR21
329
330
331 ; --
332 ; -- AUD2ENV/NR22 ($FF17)
333 ; -- Envelope (R/W)
334 ; --
335 ; -- see AUD1ENV for info
336 ; --
337 DEF rNR22 EQU $FF17
338 DEF rAUD2ENV EQU rNR22
339
340
341 ; --
342 ; -- AUD2LOW/NR23 ($FF18)
343 ; -- Frequency low byte (W)
344 ; --
345 DEF rNR23 EQU $FF18
346 DEF rAUD2LOW EQU rNR23
347
348
349 ; --
350 ; -- AUD2HIGH/NR24 ($FF19)
351 ; -- Frequency high byte (W)
352 ; --
353 ; -- see AUD1HIGH for info
354 ; --
355 DEF rNR24 EQU $FF19
356 DEF rAUD2HIGH EQU rNR24
357
358
359 ; --
360 ; -- AUD3ENA/NR30 ($FF1A)
361 ; -- Sound on/off (R/W)
362 ; --
363 ; -- Bit 7 - Sound ON/OFF (1=ON,0=OFF)
364 ; --
365 DEF rNR30 EQU $FF1A
366 DEF rAUD3ENA EQU rNR30
367
368 DEF AUD3ENA_OFF EQU %00000000
369 DEF AUD3ENA_ON EQU %10000000
370
371
372 ; --
373 ; -- AUD3LEN/NR31 ($FF1B)
374 ; -- Sound length (R/W)
375 ; --
376 ; -- Bit 7-0 - Sound length
377 ; --
378 DEF rNR31 EQU $FF1B
379 DEF rAUD3LEN EQU rNR31
380
381
382 ; --
383 ; -- AUD3LEVEL/NR32 ($FF1C)
384 ; -- Select output level
385 ; --
386 ; -- Bit 6-5 - Select output level
387 ; -- 00: 0/1 (mute)
388 ; -- 01: 1/1
389 ; -- 10: 1/2
390 ; -- 11: 1/4
391 ; --
392 DEF rNR32 EQU $FF1C
393 DEF rAUD3LEVEL EQU rNR32
394
395 DEF AUD3LEVEL_MUTE EQU %00000000
396 DEF AUD3LEVEL_100 EQU %00100000
397 DEF AUD3LEVEL_50 EQU %01000000
398 DEF AUD3LEVEL_25 EQU %01100000
399
400
401 ; --
402 ; -- AUD3LOW/NR33 ($FF1D)
403 ; -- Frequency low byte (W)
404 ; --
405 ; -- see AUD1LOW for info
406 ; --
407 DEF rNR33 EQU $FF1D
408 DEF rAUD3LOW EQU rNR33
409
410
411 ; --
412 ; -- AUD3HIGH/NR34 ($FF1E)
413 ; -- Frequency high byte (W)
414 ; --
415 ; -- see AUD1HIGH for info
416 ; --
417 DEF rNR34 EQU $FF1E
418 DEF rAUD3HIGH EQU rNR34
419
420
421 ; --
422 ; -- AUD4LEN/NR41 ($FF20)
423 ; -- Sound length (R/W)
424 ; --
425 ; -- Bit 5-0 - Sound length data (# 0-63)
426 ; --
427 DEF rNR41 EQU $FF20
428 DEF rAUD4LEN EQU rNR41
429
430
431 ; --
432 ; -- AUD4ENV/NR42 ($FF21)
433 ; -- Envelope (R/W)
434 ; --
435 ; -- see AUD1ENV for info
436 ; --
437 DEF rNR42 EQU $FF21
438 DEF rAUD4ENV EQU rNR42
439
440
441 ; --
442 ; -- AUD4POLY/NR43 ($FF22)
443 ; -- Polynomial counter (R/W)
444 ; --
445 ; -- Bit 7-4 - Selection of the shift clock frequency of the (scf)
446 ; -- polynomial counter (0000-1101)
447 ; -- freq=drf*1/2^scf (not sure)
448 ; -- Bit 3 - Selection of the polynomial counter's step
449 ; -- 0: 15 steps
450 ; -- 1: 7 steps
451 ; -- Bit 2-0 - Selection of the dividing ratio of frequencies (drf)
452 ; -- 000: f/4 001: f/8 010: f/16 011: f/24
453 ; -- 100: f/32 101: f/40 110: f/48 111: f/56 (f=4.194304 Mhz)
454 ; --
455 DEF rNR43 EQU $FF22
456 DEF rAUD4POLY EQU rNR43
457
458 DEF AUD4POLY_15STEP EQU %00000000
459 DEF AUD4POLY_7STEP EQU %00001000
460
461
462 ; --
463 ; -- AUD4GO/NR44 ($FF23)
464 ; --
465 ; -- Bit 7 - Initial (when set, sound restarts)
466 ; -- Bit 6 - Counter/consecutive selection
467 ; --
468 DEF rNR44 EQU $FF23
469 DEF rAUD4GO EQU rNR44
470
471
472 ; --
473 ; -- AUDVOL/NR50 ($FF24)
474 ; -- Channel control / ON-OFF / Volume (R/W)
475 ; --
476 ; -- Bit 7 - Vin->SO2 ON/OFF (left)
477 ; -- Bit 6-4 - SO2 output level (left speaker) (# 0-7)
478 ; -- Bit 3 - Vin->SO1 ON/OFF (right)
479 ; -- Bit 2-0 - SO1 output level (right speaker) (# 0-7)
480 ; --
481 DEF rNR50 EQU $FF24
482 DEF rAUDVOL EQU rNR50
483
484 DEF AUDVOL_VIN_LEFT EQU %10000000 ; SO2
485 DEF AUDVOL_VIN_RIGHT EQU %00001000 ; SO1
486
487
488 ; --
489 ; -- AUDTERM/NR51 ($FF25)
490 ; -- Selection of Sound output terminal (R/W)
491 ; --
492 ; -- Bit 7 - Output channel 4 to SO2 terminal (left)
493 ; -- Bit 6 - Output channel 3 to SO2 terminal (left)
494 ; -- Bit 5 - Output channel 2 to SO2 terminal (left)
495 ; -- Bit 4 - Output channel 1 to SO2 terminal (left)
496 ; -- Bit 3 - Output channel 4 to SO1 terminal (right)
497 ; -- Bit 2 - Output channel 3 to SO1 terminal (right)
498 ; -- Bit 1 - Output channel 2 to SO1 terminal (right)
499 ; -- Bit 0 - Output channel 1 to SO1 terminal (right)
500 ; --
501 DEF rNR51 EQU $FF25
502 DEF rAUDTERM EQU rNR51
503
504 ; SO2
505 DEF AUDTERM_4_LEFT EQU %10000000
506 DEF AUDTERM_3_LEFT EQU %01000000
507 DEF AUDTERM_2_LEFT EQU %00100000
508 DEF AUDTERM_1_LEFT EQU %00010000
509 ; SO1
510 DEF AUDTERM_4_RIGHT EQU %00001000
511 DEF AUDTERM_3_RIGHT EQU %00000100
512 DEF AUDTERM_2_RIGHT EQU %00000010
513 DEF AUDTERM_1_RIGHT EQU %00000001
514
515
516 ; --
517 ; -- AUDENA/NR52 ($FF26)
518 ; -- Sound on/off (R/W)
519 ; --
520 ; -- Bit 7 - All sound on/off (sets all audio regs to 0!)
521 ; -- Bit 3 - Sound 4 ON flag (read only)
522 ; -- Bit 2 - Sound 3 ON flag (read only)
523 ; -- Bit 1 - Sound 2 ON flag (read only)
524 ; -- Bit 0 - Sound 1 ON flag (read only)
525 ; --
526 DEF rNR52 EQU $FF26
527 DEF rAUDENA EQU rNR52
528
529 DEF AUDENA_ON EQU %10000000
530 DEF AUDENA_OFF EQU %00000000 ; sets all audio regs to 0!
531
532
533 ; --
534 ; -- LCDC ($FF40)
535 ; -- LCD Control (R/W)
536 ; --
537 DEF rLCDC EQU $FF40
538
539 DEF LCDCF_OFF EQU %00000000 ; LCD Control Operation
540 DEF LCDCF_ON EQU %10000000 ; LCD Control Operation
541 DEF LCDCF_WIN9800 EQU %00000000 ; Window Tile Map Display Select
542 DEF LCDCF_WIN9C00 EQU %01000000 ; Window Tile Map Display Select
543 DEF LCDCF_WINOFF EQU %00000000 ; Window Display
544 DEF LCDCF_WINON EQU %00100000 ; Window Display
545 DEF LCDCF_BLK21 EQU %00000000 ; BG & Window Tile Data Select
546 DEF LCDCF_BLK01 EQU %00010000 ; BG & Window Tile Data Select
547 DEF LCDCF_BG9800 EQU %00000000 ; BG Tile Map Display Select
548 DEF LCDCF_BG9C00 EQU %00001000 ; BG Tile Map Display Select
549 DEF LCDCF_OBJ8 EQU %00000000 ; OBJ Construction
550 DEF LCDCF_OBJ16 EQU %00000100 ; OBJ Construction
551 DEF LCDCF_OBJOFF EQU %00000000 ; OBJ Display
552 DEF LCDCF_OBJON EQU %00000010 ; OBJ Display
553 DEF LCDCF_BGOFF EQU %00000000 ; BG Display
554 DEF LCDCF_BGON EQU %00000001 ; BG Display
555
556 DEF LCDCB_ON EQU 7 ; LCD Control Operation
557 DEF LCDCB_WIN9C00 EQU 6 ; Window Tile Map Display Select
558 DEF LCDCB_WINON EQU 5 ; Window Display
559 DEF LCDCB_BLKS EQU 4 ; BG & Window Tile Data Select
560 DEF LCDCB_BG9C00 EQU 3 ; BG Tile Map Display Select
561 DEF LCDCB_OBJ16 EQU 2 ; OBJ Construction
562 DEF LCDCB_OBJON EQU 1 ; OBJ Display
563 DEF LCDCB_BGON EQU 0 ; BG Display
564 ; "Window Character Data Select" follows BG
565
566
567 ; --
568 ; -- STAT ($FF41)
569 ; -- LCDC Status (R/W)
570 ; --
571 DEF rSTAT EQU $FF41
572
573 DEF STATF_LYC EQU %01000000 ; LYC=LY Coincidence (Selectable)
574 DEF STATF_MODE10 EQU %00100000 ; Mode 10
575 DEF STATF_MODE01 EQU %00010000 ; Mode 01 (V-Blank)
576 DEF STATF_MODE00 EQU %00001000 ; Mode 00 (H-Blank)
577 DEF STATF_LYCF EQU %00000100 ; Coincidence Flag
578 DEF STATF_HBL EQU %00000000 ; H-Blank
579 DEF STATF_VBL EQU %00000001 ; V-Blank
580 DEF STATF_OAM EQU %00000010 ; OAM-RAM is used by system
581 DEF STATF_LCD EQU %00000011 ; Both OAM and VRAM used by system
582 DEF STATF_BUSY EQU %00000010 ; When set, VRAM access is unsafe
583
584 DEF STATB_LYC EQU 6
585 DEF STATB_MODE10 EQU 5
586 DEF STATB_MODE01 EQU 4
587 DEF STATB_MODE00 EQU 3
588 DEF STATB_LYCF EQU 2
589 DEF STATB_BUSY EQU 1
590
591 ; --
592 ; -- SCY ($FF42)
593 ; -- Scroll Y (R/W)
594 ; --
595 DEF rSCY EQU $FF42
596
597
598 ; --
599 ; -- SCX ($FF43)
600 ; -- Scroll X (R/W)
601 ; --
602 DEF rSCX EQU $FF43
603
604
605 ; --
606 ; -- LY ($FF44)
607 ; -- LCDC Y-Coordinate (R)
608 ; --
609 ; -- Values range from 0->153. 144->153 is the VBlank period.
610 ; --
611 DEF rLY EQU $FF44
612
613
614 ; --
615 ; -- LYC ($FF45)
616 ; -- LY Compare (R/W)
617 ; --
618 ; -- When LY==LYC, STATF_LYCF will be set in STAT
619 ; --
620 DEF rLYC EQU $FF45
621
622
623 ; --
624 ; -- DMA ($FF46)
625 ; -- DMA Transfer and Start Address (W)
626 ; --
627 DEF rDMA EQU $FF46
628
629
630 ; --
631 ; -- BGP ($FF47)
632 ; -- BG Palette Data (W)
633 ; --
634 ; -- Bit 7-6 - Intensity for %11
635 ; -- Bit 5-4 - Intensity for %10
636 ; -- Bit 3-2 - Intensity for %01
637 ; -- Bit 1-0 - Intensity for %00
638 ; --
639 DEF rBGP EQU $FF47
640
641
642 ; --
643 ; -- OBP0 ($FF48)
644 ; -- Object Palette 0 Data (W)
645 ; --
646 ; -- See BGP for info
647 ; --
648 DEF rOBP0 EQU $FF48
649
650
651 ; --
652 ; -- OBP1 ($FF49)
653 ; -- Object Palette 1 Data (W)
654 ; --
655 ; -- See BGP for info
656 ; --
657 DEF rOBP1 EQU $FF49
658
659
660 ; --
661 ; -- WY ($FF4A)
662 ; -- Window Y Position (R/W)
663 ; --
664 ; -- 0 <= WY <= 143
665 ; -- When WY = 0, the window is displayed from the top edge of the LCD screen.
666 ; --
667 DEF rWY EQU $FF4A
668
669
670 ; --
671 ; -- WX ($FF4B)
672 ; -- Window X Position (R/W)
673 ; --
674 ; -- 7 <= WX <= 166
675 ; -- When WX = 7, the window is displayed from the left edge of the LCD screen.
676 ; -- Values of 0-6 and 166 are unreliable due to hardware bugs.
677 ; --
678 DEF rWX EQU $FF4B
679
680 DEF WX_OFS EQU 7 ; add this to a screen position to get a WX position
681
682
683 ; --
684 ; -- SPEED ($FF4D)
685 ; -- Select CPU Speed (R/W)
686 ; --
687 DEF rKEY1 EQU $FF4D
688 DEF rSPD EQU rKEY1
689
690 DEF KEY1F_DBLSPEED EQU %10000000 ; 0=Normal Speed, 1=Double Speed (R)
691 DEF KEY1F_PREPARE EQU %00000001 ; 0=No, 1=Prepare (R/W)
692
693
694 ; --
695 ; -- VBK ($FF4F)
696 ; -- Select Video RAM Bank (R/W)
697 ; --
698 ; -- Bit 0 - Bank Specification (0: Specify Bank 0; 1: Specify Bank 1)
699 ; --
700 DEF rVBK EQU $FF4F
701
702
703 ; --
704 ; -- HDMA1 ($FF51)
705 ; -- High byte for Horizontal Blanking/General Purpose DMA source address (W)
706 ; -- CGB Mode Only
707 ; --
708 DEF rHDMA1 EQU $FF51
709
710
711 ; --
712 ; -- HDMA2 ($FF52)
713 ; -- Low byte for Horizontal Blanking/General Purpose DMA source address (W)
714 ; -- CGB Mode Only
715 ; --
716 DEF rHDMA2 EQU $FF52
717
718
719 ; --
720 ; -- HDMA3 ($FF53)
721 ; -- High byte for Horizontal Blanking/General Purpose DMA destination address (W)
722 ; -- CGB Mode Only
723 ; --
724 DEF rHDMA3 EQU $FF53
725
726
727 ; --
728 ; -- HDMA4 ($FF54)
729 ; -- Low byte for Horizontal Blanking/General Purpose DMA destination address (W)
730 ; -- CGB Mode Only
731 ; --
732 DEF rHDMA4 EQU $FF54
733
734
735 ; --
736 ; -- HDMA5 ($FF55)
737 ; -- Transfer length (in tiles minus 1)/mode/start for Horizontal Blanking, General Purpose DMA (R/W)
738 ; -- CGB Mode Only
739 ; --
740 DEF rHDMA5 EQU $FF55
741
742 DEF HDMA5F_MODE_GP EQU %00000000 ; General Purpose DMA (W)
743 DEF HDMA5F_MODE_HBL EQU %10000000 ; HBlank DMA (W)
744 DEF HDMA5B_MODE EQU 7 ; DMA mode select (W)
745
746 ; -- Once DMA has started, use HDMA5F_BUSY to check when the transfer is complete
747 DEF HDMA5F_BUSY EQU %10000000 ; 0=Busy (DMA still in progress), 1=Transfer complete (R)
748
749
750 ; --
751 ; -- RP ($FF56)
752 ; -- Infrared Communications Port (R/W)
753 ; -- CGB Mode Only
754 ; --
755 DEF rRP EQU $FF56
756
757 DEF RPF_ENREAD EQU %11000000
758 DEF RPF_DATAIN EQU %00000010 ; 0=Receiving IR Signal, 1=Normal
759 DEF RPF_WRITE_HI EQU %00000001
760 DEF RPF_WRITE_LO EQU %00000000
761
762 DEF RPB_LED_ON EQU 0
763 DEF RPB_DATAIN EQU 1
764
765
766 ; --
767 ; -- BCPS/BGPI ($FF68)
768 ; -- Background Color Palette Specification (aka Background Palette Index) (R/W)
769 ; --
770 DEF rBCPS EQU $FF68
771 DEF rBGPI EQU rBCPS
772
773 DEF BCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
774 DEF BCPSB_AUTOINC EQU 7
775 DEF BGPIF_AUTOINC EQU BCPSF_AUTOINC
776 DEF BGPIB_AUTOINC EQU BCPSB_AUTOINC
777
778
779 ; --
780 ; -- BCPD/BGPD ($FF69)
781 ; -- Background Color Palette Data (aka Background Palette Data) (R/W)
782 ; --
783 DEF rBCPD EQU $FF69
784 DEF rBGPD EQU rBCPD
785
786
787 ; --
788 ; -- OCPS/OBPI ($FF6A)
789 ; -- Object Color Palette Specification (aka Object Background Palette Index) (R/W)
790 ; --
791 DEF rOCPS EQU $FF6A
792 DEF rOBPI EQU rOCPS
793
794 DEF OCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
795 DEF OCPSB_AUTOINC EQU 7
796 DEF OBPIF_AUTOINC EQU OCPSF_AUTOINC
797 DEF OBPIB_AUTOINC EQU OCPSB_AUTOINC
798
799
800 ; --
801 ; -- OCPD/OBPD ($FF6B)
802 ; -- Object Color Palette Data (aka Object Background Palette Data) (R/W)
803 ; --
804 DEF rOCPD EQU $FF6B
805 DEF rOBPD EQU rOCPD
806
807
808 ; --
809 ; -- OPRI ($FF6C)
810 ; -- Object Priority Mode (R/W)
811 ; -- CGB Only
812
813 ; --
814 ; -- Priority can be changed only from the boot ROM
815 ; --
816 DEF rOPRI EQU $FF6C
817
818 DEF OPRI_OAM EQU 0 ; Prioritize objects by location in OAM (CGB Mode default)
819 DEF OPRI_COORD EQU 1 ; Prioritize objects by x-coordinate (Non-CGB Mode default)
820
821
822
823 ; --
824 ; -- SMBK/SVBK ($FF70)
825 ; -- Select Main RAM Bank (R/W)
826 ; --
827 ; -- Bit 2-0 - Bank Specification (0,1: Specify Bank 1; 2-7: Specify Banks 2-7)
828 ; --
829 DEF rSVBK EQU $FF70
830 DEF rSMBK EQU rSVBK
831
832
833 ; --
834 ; -- PCM12 ($FF76)
835 ; -- Sound channel 1&2 PCM amplitude (R)
836 ; --
837 ; -- Bit 7-4 - Copy of sound channel 2's PCM amplitude
838 ; -- Bit 3-0 - Copy of sound channel 1's PCM amplitude
839 ; --
840 DEF rPCM12 EQU $FF76
841
842
843 ; --
844 ; -- PCM34 ($FF77)
845 ; -- Sound channel 3&4 PCM amplitude (R)
846 ; --
847 ; -- Bit 7-4 - Copy of sound channel 4's PCM amplitude
848 ; -- Bit 3-0 - Copy of sound channel 3's PCM amplitude
849 ; --
850 DEF rPCM34 EQU $FF77
851
852
853 ; --
854 ; -- IE ($FFFF)
855 ; -- Interrupt Enable (R/W)
856 ; --
857 DEF rIE EQU $FFFF
858
859 DEF IEF_HILO EQU %00010000 ; Transition from High to Low of Pin number P10-P13
860 DEF IEF_SERIAL EQU %00001000 ; Serial I/O transfer end
861 DEF IEF_TIMER EQU %00000100 ; Timer Overflow
862 DEF IEF_STAT EQU %00000010 ; STAT
863 DEF IEF_VBLANK EQU %00000001 ; V-Blank
864
865 DEF IEB_HILO EQU 4
866 DEF IEB_SERIAL EQU 3
867 DEF IEB_TIMER EQU 2
868 DEF IEB_STAT EQU 1
869 DEF IEB_VBLANK EQU 0
870
871
872 ;***************************************************************************
873 ;*
874 ;* Flags common to multiple sound channels
875 ;*
876 ;***************************************************************************
877
878 ; --
879 ; -- Square wave duty cycle
880 ; --
881 ; -- Can be used with AUD1LEN and AUD2LEN
882 ; -- See AUD1LEN for more info
883 ; --
884 DEF AUDLEN_DUTY_12_5 EQU %00000000 ; 12.5%
885 DEF AUDLEN_DUTY_25 EQU %01000000 ; 25%
886 DEF AUDLEN_DUTY_50 EQU %10000000 ; 50%
887 DEF AUDLEN_DUTY_75 EQU %11000000 ; 75%
888
889
890 ; --
891 ; -- Audio envelope flags
892 ; --
893 ; -- Can be used with AUD1ENV, AUD2ENV, AUD4ENV
894 ; -- See AUD1ENV for more info
895 ; --
896 DEF AUDENV_UP EQU %00001000
897 DEF AUDENV_DOWN EQU %00000000
898
899
900 ; --
901 ; -- Audio trigger flags
902 ; --
903 ; -- Can be used with AUD1HIGH, AUD2HIGH, AUD3HIGH
904 ; -- See AUD1HIGH for more info
905 ; --
906 DEF AUDHIGH_RESTART EQU %10000000
907 DEF AUDHIGH_LENGTH_ON EQU %01000000
908 DEF AUDHIGH_LENGTH_OFF EQU %00000000
909
910
911 ;***************************************************************************
912 ;*
913 ;* CPU values on bootup (a=type, b=qualifier)
914 ;*
915 ;***************************************************************************
916
917 DEF BOOTUP_A_DMG EQU $01 ; Dot Matrix Game
918 DEF BOOTUP_A_CGB EQU $11 ; Color GameBoy
919 DEF BOOTUP_A_MGB EQU $FF ; Mini GameBoy (Pocket GameBoy)
920
921 ; if a=BOOTUP_A_CGB, bit 0 in b can be checked to determine if real CGB or
922 ; other system running in GBC mode
923 DEF BOOTUP_B_CGB EQU %00000000
924 DEF BOOTUP_B_AGB EQU %00000001 ; GBA, GBA SP, Game Boy Player, or New GBA SP
925
926
927 ;***************************************************************************
928 ;*
929 ;* Interrupt vector addresses
930 ;*
931 ;***************************************************************************
932
933 DEF INT_HANDLER_VBLANK EQU $0040
934 DEF INT_HANDLER_STAT EQU $0048
935 DEF INT_HANDLER_TIMER EQU $0050
936 DEF INT_HANDLER_SERIAL EQU $0058
937 DEF INT_HANDLER_JOYPAD EQU $0060
938
939
940 ;***************************************************************************
941 ;*
942 ;* Header
943 ;*
944 ;***************************************************************************
945
946 ;*
947 ;* Nintendo scrolling logo
948 ;* (Code won't work on a real GameBoy)
949 ;* (if next lines are altered.)
950 MACRO NINTENDO_LOGO
951 DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D
952 DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99
953 DB $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E
954 ENDM
955
956 ; $0143 Color GameBoy compatibility code
957 DEF CART_COMPATIBLE_DMG EQU $00
958 DEF CART_COMPATIBLE_DMG_GBC EQU $80
959 DEF CART_COMPATIBLE_GBC EQU $C0
960
961 ; $0146 GameBoy/Super GameBoy indicator
962 DEF CART_INDICATOR_GB EQU $00
963 DEF CART_INDICATOR_SGB EQU $03
964
965 ; $0147 Cartridge type
966 DEF CART_ROM EQU $00
967 DEF CART_ROM_MBC1 EQU $01
968 DEF CART_ROM_MBC1_RAM EQU $02
969 DEF CART_ROM_MBC1_RAM_BAT EQU $03
970 DEF CART_ROM_MBC2 EQU $05
971 DEF CART_ROM_MBC2_BAT EQU $06
972 DEF CART_ROM_RAM EQU $08
973 DEF CART_ROM_RAM_BAT EQU $09
974 DEF CART_ROM_MMM01 EQU $0B
975 DEF CART_ROM_MMM01_RAM EQU $0C
976 DEF CART_ROM_MMM01_RAM_BAT EQU $0D
977 DEF CART_ROM_MBC3_BAT_RTC EQU $0F
978 DEF CART_ROM_MBC3_RAM_BAT_RTC EQU $10
979 DEF CART_ROM_MBC3 EQU $11
980 DEF CART_ROM_MBC3_RAM EQU $12
981 DEF CART_ROM_MBC3_RAM_BAT EQU $13
982 DEF CART_ROM_MBC5 EQU $19
983 DEF CART_ROM_MBC5_BAT EQU $1A
984 DEF CART_ROM_MBC5_RAM_BAT EQU $1B
985 DEF CART_ROM_MBC5_RUMBLE EQU $1C
986 DEF CART_ROM_MBC5_RAM_RUMBLE EQU $1D
987 DEF CART_ROM_MBC5_RAM_BAT_RUMBLE EQU $1E
988 DEF CART_ROM_MBC7_RAM_BAT_GYRO EQU $22
989 DEF CART_ROM_POCKET_CAMERA EQU $FC
990 DEF CART_ROM_BANDAI_TAMA5 EQU $FD
991 DEF CART_ROM_HUDSON_HUC3 EQU $FE
992 DEF CART_ROM_HUDSON_HUC1 EQU $FF
993
994 ; $0148 ROM size
995 ; these are kilobytes
996 DEF CART_ROM_32KB EQU $00 ; 2 banks
997 DEF CART_ROM_64KB EQU $01 ; 4 banks
998 DEF CART_ROM_128KB EQU $02 ; 8 banks
999 DEF CART_ROM_256KB EQU $03 ; 16 banks
1000 DEF CART_ROM_512KB EQU $04 ; 32 banks
1001 DEF CART_ROM_1024KB EQU $05 ; 64 banks
1002 DEF CART_ROM_2048KB EQU $06 ; 128 banks
1003 DEF CART_ROM_4096KB EQU $07 ; 256 banks
1004 DEF CART_ROM_8192KB EQU $08 ; 512 banks
1005 DEF CART_ROM_1152KB EQU $52 ; 72 banks
1006 DEF CART_ROM_1280KB EQU $53 ; 80 banks
1007 DEF CART_ROM_1536KB EQU $54 ; 96 banks
1008
1009 ; $0149 SRAM size
1010 ; these are kilobytes
1011 DEF CART_SRAM_NONE EQU 0
1012 DEF CART_SRAM_8KB EQU 2 ; 1 bank
1013 DEF CART_SRAM_32KB EQU 3 ; 4 banks
1014 DEF CART_SRAM_128KB EQU 4 ; 16 banks
1015
1016 ; $014A Destination code
1017 DEF CART_DEST_JAPANESE EQU $00
1018 DEF CART_DEST_NON_JAPANESE EQU $01
1019
1020
1021 ;***************************************************************************
1022 ;*
1023 ;* Keypad related
1024 ;*
1025 ;***************************************************************************
1026
1027 DEF PADF_DOWN EQU $80
1028 DEF PADF_UP EQU $40
1029 DEF PADF_LEFT EQU $20
1030 DEF PADF_RIGHT EQU $10
1031 DEF PADF_START EQU $08
1032 DEF PADF_SELECT EQU $04
1033 DEF PADF_B EQU $02
1034 DEF PADF_A EQU $01
1035
1036 DEF PADB_DOWN EQU $7
1037 DEF PADB_UP EQU $6
1038 DEF PADB_LEFT EQU $5
1039 DEF PADB_RIGHT EQU $4
1040 DEF PADB_START EQU $3
1041 DEF PADB_SELECT EQU $2
1042 DEF PADB_B EQU $1
1043 DEF PADB_A EQU $0
1044
1045
1046 ;***************************************************************************
1047 ;*
1048 ;* Screen related
1049 ;*
1050 ;***************************************************************************
1051
1052 DEF SCRN_X EQU 160 ; Width of screen in pixels
1053 DEF SCRN_Y EQU 144 ; Height of screen in pixels. Also corresponds to the value in LY at the beginning of VBlank.
1054 DEF SCRN_X_B EQU 20 ; Width of screen in bytes
1055 DEF SCRN_Y_B EQU 18 ; Height of screen in bytes
1056
1057 DEF SCRN_VX EQU 256 ; Virtual width of screen in pixels
1058 DEF SCRN_VY EQU 256 ; Virtual height of screen in pixels
1059 DEF SCRN_VX_B EQU 32 ; Virtual width of screen in bytes
1060 DEF SCRN_VY_B EQU 32 ; Virtual height of screen in bytes
1061
1062
1063 ;***************************************************************************
1064 ;*
1065 ;* OAM related
1066 ;*
1067 ;***************************************************************************
1068
1069 ; OAM attributes
1070 ; each entry in OAM RAM is 4 bytes (sizeof_OAM_ATTRS)
1071 RSRESET
1072 DEF OAMA_Y RB 1 ; y pos plus 16
1073 DEF OAMA_X RB 1 ; x pos plus 8
1074 DEF OAMA_TILEID RB 1 ; tile id
1075 DEF OAMA_FLAGS RB 1 ; flags (see below)
1076 DEF sizeof_OAM_ATTRS RB 0
1077
1078 DEF OAM_Y_OFS EQU 16 ; add this to a screen-relative Y position to get an OAM Y position
1079 DEF OAM_X_OFS EQU 8 ; add this to a screen-relative X position to get an OAM X position
1080
1081 DEF OAM_COUNT EQU 40 ; number of OAM entries in OAM RAM
1082
1083 ; flags
1084 DEF OAMF_PRI EQU %10000000 ; Priority
1085 DEF OAMF_YFLIP EQU %01000000 ; Y flip
1086 DEF OAMF_XFLIP EQU %00100000 ; X flip
1087 DEF OAMF_PAL0 EQU %00000000 ; Palette number; 0,1 (DMG)
1088 DEF OAMF_PAL1 EQU %00010000 ; Palette number; 0,1 (DMG)
1089 DEF OAMF_BANK0 EQU %00000000 ; Bank number; 0,1 (GBC)
1090 DEF OAMF_BANK1 EQU %00001000 ; Bank number; 0,1 (GBC)
1091
1092 DEF OAMF_PALMASK EQU %00000111 ; Palette (GBC)
1093
1094 DEF OAMB_PRI EQU 7 ; Priority
1095 DEF OAMB_YFLIP EQU 6 ; Y flip
1096 DEF OAMB_XFLIP EQU 5 ; X flip
1097 DEF OAMB_PAL1 EQU 4 ; Palette number; 0,1 (DMG)
1098 DEF OAMB_BANK1 EQU 3 ; Bank number; 0,1 (GBC)
1099
1100
1101 ; Deprecated constants. Please avoid using.
1102
1103 DEF IEF_LCDC EQU %00000010 ; LCDC (see STAT)
1104 DEF _VRAM8000 EQU _VRAM
1105 DEF _VRAM8800 EQU _VRAM+$800
1106 DEF _VRAM9000 EQU _VRAM+$1000
1107 DEF CART_SRAM_2KB EQU 1 ; 1 incomplete bank
1108 DEF LCDCF_BG8800 EQU %00000000 ; BG & Window Tile Data Select
1109 DEF LCDCF_BG8000 EQU %00010000 ; BG & Window Tile Data Select
1110 DEF LCDCB_BG8000 EQU 4 ; BG & Window Tile Data Select
1111
1112
1113 ENDC ;HARDWARE_INC
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