gbdk-2020 | GameBoy Development Kit |
| download: https://git.y1.nz/archives/gbdk.tar.gz | |
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gbdk-lib/include/gb/hardware.h
1 /** @file gb/hardware.h
2 Defines that let the GB's hardware registers be accessed
3 from C.
4
5 See the @ref Pandocs for more details on each register.
6 */
7 #ifndef _HARDWARE_H
8 #define _HARDWARE_H
9
10 #include <types.h>
11
12 #define __BYTES extern UBYTE
13 #define __BYTE_REG extern volatile UBYTE
14 #define __REG extern volatile SFR
15
16 /** Memory map */
17
18 __BYTES _VRAM[];
19 __BYTES _VRAM8000[];
20 __BYTES _VRAM8800[];
21 __BYTES _VRAM9000[];
22 __BYTES _SCRN0[];
23 __BYTES _SCRN1[];
24 __BYTES _SRAM[];
25 __BYTES _RAM[];
26 __BYTES _RAMBANK[];
27 __BYTES _OAMRAM[];
28 __BYTE_REG _IO[];
29 __BYTE_REG _AUD3WAVERAM[];
30 __BYTE_REG _HRAM[];
31
32 /** MBC5 registers */
33
34 __BYTE_REG rRAMG;
35 __BYTE_REG rROMB0;
36 __BYTE_REG rROMB1;
37 __BYTE_REG rRAMB;
38
39 /** MBC7 registers */
40
41 __BYTE_REG rMBC7_SRAM_ENABLE_1;
42 __BYTE_REG rMBC7_SRAM_ENABLE_2;
43 __BYTE_REG rMBC7_LATCH_1;
44 __BYTE_REG rMBC7_LATCH_2;
45 __BYTE_REG rMBC7_ACCEL_X_LO;
46 __BYTE_REG rMBC7_ACCEL_X_HI;
47 __BYTE_REG rMBC7_ACCEL_Y_LO;
48 __BYTE_REG rMBC7_ACCEL_Y_HI;
49
50 #define MBC7_LATCH_ERASE 0x55u
51 #define MBC7_LATCH_CAPTURE 0xAAu
52 #define MBC7_SRAM_ENABLE_KEY_1 0x0Au
53 #define MBC7_SRAM_ENABLE_KEY_2 0x40u
54
55 /** IO Registers */
56
57 __REG P1_REG; /**< Joystick register @see joypad(), add_JOY(), IEF_HILO, P1F_5, P1F_4, P1F_3, P1F_2, P1F_1, P1F_0, P1F_GET_DPAD, P1F_GET_BTN, P1F_GET_NONE */
58 #define rP1 P1_REG
59
60 #define P1F_5 0b00100000
61 #define P1F_4 0b00010000
62 #define P1F_3 0b00001000
63 #define P1F_2 0b00000100
64 #define P1F_1 0b00000010
65 #define P1F_0 0b00000001
66
67 #define P1F_GET_DPAD P1F_5
68 #define P1F_GET_BTN P1F_4
69 #define P1F_GET_NONE (P1F_4 | P1F_5)
70
71 __REG SB_REG; /**< Serial IO data buffer */
72 #define rSB SB_REG
73 __REG SC_REG; /**< Serial IO control register */
74 #define rSC SC_REG
75
76 #define SIOF_XFER_START 0b10000000 /**< Serial IO: Start Transfer. Automatically cleared at the end of transfer */
77 #define SIOF_CLOCK_INT 0b00000001 /**< Serial IO: Use Internal clock */
78 #define SIOF_CLOCK_EXT 0b00000000 /**< Serial IO: Use External clock */
79 #define SIOF_SPEED_1X 0b00000000 /**< Serial IO: If internal clock then 8KHz mode, 1KB/s (16Khz in CGB high-speed mode, 2KB/s) */
80 #define SIOF_SPEED_32X 0b00000010 /**< Serial IO: **CGB-Mode ONLY** If internal clock then 256KHz mode, 32KB/s (512KHz in CGB high-speed mode, 64KB/s) */
81 #define SIOF_B_CLOCK 0
82 #define SIOF_B_SPEED 1
83 #define SIOF_B_XFER_START 7
84 #define SCF_START SIOF_XFER_START
85 #define SCF_SOURCE SIOF_CLOCK_INT
86 #define SCF_SPEED SIOF_SPEED_32X
87
88 __REG DIV_REG; /**< Divider register */
89 #define rDIV DIV_REG
90 __REG TIMA_REG; /**< Timer counter */
91 #define rTIMA TIMA_REG
92 __REG TMA_REG; /**< Timer modulo */
93 #define rTMA TMA_REG
94 __REG TAC_REG; /**< Timer control */
95 #define rTAC TAC_REG
96
97 #define TACF_START 0b00000100
98 #define TACF_STOP 0b00000000
99 #define TACF_4KHZ 0b00000000
100 #define TACF_16KHZ 0b00000011
101 #define TACF_65KHZ 0b00000010
102 #define TACF_262KHZ 0b00000001
103
104 __REG IF_REG; /**< Interrupt flags: @ref IEF_HILO, @ref IEF_SERIAL, @ref IEF_TIMER, @ref IEF_STAT, @ref IEF_VBLANK */
105 #define rIF IF_REG
106
107 __REG NR10_REG; /**< Sound Channel 1, NR10: Sweep */
108 #define rAUD1SWEEP NR10_REG /**< Sound Channel 1, NR10: Sweep */
109 #define AUD1SWEEP_UP 0b00000000 /**< For Sound Channel 1, NR10: Sweep Addition, period increases */
110 #define AUD1SWEEP_DOWN 0b00001000 /**< For Sound Channel 1, NR10: Sweep Subtraction, period decreases */
111 #define AUD1SWEEP_TIME(x) ((x) << 4) /**< For Sound Channel 1, NR10: Sweep Time/Pace, Range: 0-7 */
112 #define AUD1SWEEP_LENGTH(x) (x) /**< For Sound Channel 1, NR10: Sweep Length/Individual step, Range: 0-7 */
113 __REG NR11_REG; /**< Sound Channel 1, NR11: Sound length/Wave pattern duty */
114 #define rAUD1LEN NR11_REG /**< Sound Channel 1, NR11: Sound length/Wave pattern duty */
115 __REG NR12_REG; /**< Sound Channel 1, NR12: Volume Envelope */
116 #define rAUD1ENV NR12_REG /**< Sound Channel 1, NR12: Volume Envelope */
117 __REG NR13_REG; /**< Sound Channel 1, NR13: Frequency Low */
118 #define rAUD1LOW NR13_REG /**< Sound Channel 1, NR13: Frequency Low */
119 __REG NR14_REG; /**< Sound Channel 1, NR14: Frequency High */
120 #define rAUD1HIGH NR14_REG /**< Sound Channel 1, NR14: Frequency High */
121
122 __REG NR21_REG; /**< Sound Channel 2, NR21_REG: Tone */
123 #define rAUD2LEN NR21_REG /**< Sound Channel 2, NR21_REG: Tone */
124 __REG NR22_REG; /**< Sound Channel 2, NR22_REG: Volume Envelope */
125 #define rAUD2ENV NR22_REG /**< Sound Channel 2, NR22_REG: Volume Envelope */
126 __REG NR23_REG; /**< Sound Channel 2, NR23_REG: Frequency data Low */
127 #define rAUD2LOW NR23_REG /**< Sound Channel 2, NR23_REG: Frequency data Low */
128 __REG NR24_REG; /**< Sound Channel 2, NR24_REG: Frequency data High */
129 #define rAUD2HIGH NR24_REG /**< Sound Channel 2, NR24_REG: Frequency data High */
130
131 __REG NR30_REG; /**< Sound Channel 3, NR30_REG: Sound on/off */
132 #define rAUD3ENA NR30_REG /**< Sound Channel 3, NR30_REG: Sound on/off */
133 __REG NR31_REG; /**< Sound Channel 3, NR31_REG: Sound Length */
134 #define rAUD3LEN NR31_REG /**< Sound Channel 3, NR31_REG: Sound Length */
135 __REG NR32_REG; /**< Sound Channel 3, NR32_REG: Select output level */
136 #define rAUD3LEVEL NR32_REG/**< Sound Channel 3, NR32_REG: Select output level */
137 __REG NR33_REG; /**< Sound Channel 3, NR33_REG: Frequency data Low */
138 #define rAUD3LOW NR33_REG /**< Sound Channel 3, NR33_REG: Frequency data Low */
139 __REG NR34_REG; /**< Sound Channel 3, NR34_REG: Frequency data High */
140 #define rAUD3HIGH NR34_REG /**< Sound Channel 3, NR34_REG: Frequency data High */
141
142 __REG NR41_REG; /**< Sound Channel 4, NR41_REG: Sound Length */
143 #define rAUD4LEN NR41_REG /**< Sound Channel 4, NR41_REG: Sound Length */
144 __REG NR42_REG; /**< Sound Channel 4, NR42_REG: Volume Envelope */
145 #define rAUD4ENV NR42_REG /**< Sound Channel 4, NR42_REG: Volume Envelope */
146 __REG NR43_REG; /**< Sound Channel 4, NR43_REG: Polynomial Counter */
147 #define rAUD4POLY NR43_REG /**< Sound Channel 4, NR43_REG: Polynomial Counter */
148 #define AUD4POLY_WIDTH_15BIT 0x00 /**< For Sound Channel 4, NR43_REG: Polynomial counter use 15 steps */
149 #define AUD4POLY_WIDTH_7BIT 0x08 /**< For Sound Channel 4, NR43_REG: Polynomial counter use 7 steps */
150 __REG NR44_REG; /**< Sound Channel 4, NR44_REG: Counter / Consecutive and Initial */
151 #define rAUD4GO NR44_REG /**< Sound Channel 4, NR44_REG: Counter / Consecutive and Initial */
152
153 __REG NR50_REG; /**< Sound Master Volume, NR50: Volume and Cart external sound input (VIN) */
154 #define rAUDVOL NR50_REG /**< Sound Master Volume, NR50: Volume and Cart external sound input (VIN) */
155
156 #define AUDVOL_VOL_LEFT(x) ((x) << 4) /**< For Sound Master Volume, NR50: Left Volume, Range: 0-7 */
157 #define AUDVOL_VOL_RIGHT(x) ((x)) /**< For Sound Master Volume, NR50: Right Volume, Range: 0-7 */
158 #define AUDVOL_VIN_LEFT 0b10000000 /**< For Sound Master Volume, NR50: Cart external sound input (VIN) Left bit, 1 = ON, 0 = OFF */
159 #define AUDVOL_VIN_RIGHT 0b00001000 /**< For Sound Master Volume, NR50: Cart external sound input (VIN) Right bit, 1 = ON, 0 = OFF */
160
161 __REG NR51_REG; /**< Sound Panning, NR51: Enable/disable left and right output for sound channels */
162 #define rAUDTERM NR51_REG /**< Sound Panning, NR51: Enable/disable left and right output for sound channels */
163
164 #define AUDTERM_4_LEFT 0b10000000 /**< For Sound Panning, NR51: Channel 4 Left bit, 1 = ON, 0 = OFF */
165 #define AUDTERM_3_LEFT 0b01000000 /**< For Sound Panning, NR51: Channel 3 Left bit, 1 = ON, 0 = OFF */
166 #define AUDTERM_2_LEFT 0b00100000 /**< For Sound Panning, NR51: Channel 2 Left bit, 1 = ON, 0 = OFF */
167 #define AUDTERM_1_LEFT 0b00010000 /**< For Sound Panning, NR51: Channel 1 Left bit, 1 = ON, 0 = OFF */
168 #define AUDTERM_4_RIGHT 0b00001000 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
169 #define AUDTERM_3_RIGHT 0b00000100 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
170 #define AUDTERM_2_RIGHT 0b00000010 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
171 #define AUDTERM_1_RIGHT 0b00000001 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
172
173 __REG NR52_REG; /**< Sound Master Control, NR52: ON / OFF */
174 #define rAUDENA NR52_REG /**< Sound Master Control, NR52: ON / OFF */
175
176 #define AUDENA_ON 0b10000000 /**< For Sound Master Control, NR52: Sound ON */
177 #define AUDENA_OFF 0b00000000 /**< For Sound Master Control, NR52: Sound OFF */
178
179 __BYTE_REG AUD3WAVE[16];
180 __BYTE_REG PCM_SAMPLE[16];
181
182 __REG LCDC_REG; /**< LCD control */
183 #define rLCDC LCDC_REG
184
185 #if defined(__TARGET_ap)
186 #define LCDCF_OFF 0b00000000
187 #define LCDCF_ON 0b00000001
188 #define LCDCF_WIN9800 0b00000000
189 #define LCDCF_WIN9C00 0b00000010
190 #define LCDCF_WINOFF 0b00000000
191 #define LCDCF_WINON 0b00000100
192 #define LCDCF_BG8800 0b00000000
193 #define LCDCF_BG8000 0b00001000
194 #define LCDCF_BG9800 0b00000000
195 #define LCDCF_BG9C00 0b00010000
196 #define LCDCF_OBJ8 0b00000000
197 #define LCDCF_OBJ16 0b00100000
198 #define LCDCF_OBJOFF 0b00000000
199 #define LCDCF_OBJON 0b01000000
200 #define LCDCF_BGOFF 0b00000000
201 #define LCDCF_BGON 0b10000000
202 #define LCDCF_B_ON 0
203 #define LCDCF_B_WIN9C00 1
204 #define LCDCF_B_WINON 2
205 #define LCDCF_B_BG8000 3
206 #define LCDCF_B_BG9C00 4
207 #define LCDCF_B_OBJ16 5
208 #define LCDCF_B_OBJON 6
209 #define LCDCF_B_BGON 7
210 #elif defined(__TARGET_duck)
211 #define LCDCF_OFF 0b00000000
212 #define LCDCF_ON 0b10000000
213 #define LCDCF_WIN9800 0b00000000
214 #define LCDCF_WIN9C00 0b00001000
215 #define LCDCF_WINOFF 0b00000000
216 #define LCDCF_WINON 0b00100000
217 #define LCDCF_BG8800 0b00000000
218 #define LCDCF_BG8000 0b00010000
219 #define LCDCF_BG9800 0b00000000
220 #define LCDCF_BG9C00 0b00000100
221 #define LCDCF_OBJ8 0b00000000
222 #define LCDCF_OBJ16 0b00000010
223 #define LCDCF_OBJOFF 0b00000000
224 #define LCDCF_OBJON 0b00000001
225 #define LCDCF_BGOFF 0b00000000
226 #define LCDCF_BGON 0b01000000
227 #define LCDCF_B_ON 7
228 #define LCDCF_B_WIN9C00 3
229 #define LCDCF_B_WINON 5
230 #define LCDCF_B_BG8000 4
231 #define LCDCF_B_BG9C00 2
232 #define LCDCF_B_OBJ16 1
233 #define LCDCF_B_OBJON 0
234 #define LCDCF_B_BGON 6
235 #else
236 #define LCDCF_OFF 0b00000000 /**< LCD Control: Off */
237 #define LCDCF_ON 0b10000000 /**< LCD Control: On */
238 #define LCDCF_WIN9800 0b00000000 /**< Window Tile Map: Use 9800 Region */
239 #define LCDCF_WIN9C00 0b01000000 /**< Window Tile Map: Use 9C00 Region */
240 #define LCDCF_WINOFF 0b00000000 /**< Window Display: Hidden */
241 #define LCDCF_WINON 0b00100000 /**< Window Display: Visible */
242 #define LCDCF_BG8800 0b00000000 /**< BG & Window Tile Data: Use 8800 Region */
243 #define LCDCF_BG8000 0b00010000 /**< BG & Window Tile Data: Use 8000 Region */
244 #define LCDCF_BG9800 0b00000000 /**< BG Tile Map: use 9800 Region */
245 #define LCDCF_BG9C00 0b00001000 /**< BG Tile Map: use 9C00 Region */
246 #define LCDCF_OBJ8 0b00000000 /**< Sprites Size: 8x8 pixels */
247 #define LCDCF_OBJ16 0b00000100 /**< Sprites Size: 8x16 pixels */
248 #define LCDCF_OBJOFF 0b00000000 /**< Sprites Display: Hidden */
249 #define LCDCF_OBJON 0b00000010 /**< Sprites Display: Visible */
250 #define LCDCF_BGOFF 0b00000000 /**< Background Display: Hidden */
251 #define LCDCF_BGON 0b00000001 /**< Background Display: Visible */
252 #define LCDCF_B_ON 7 /**< Bit for LCD On/Off Select */
253 #define LCDCF_B_WIN9C00 6 /**< Bit for Window Tile Map Region Select */
254 #define LCDCF_B_WINON 5 /**< Bit for Window Display On/Off Control */
255 #define LCDCF_B_BG8000 4 /**< Bit for BG & Window Tile Data Region Select */
256 #define LCDCF_B_BG9C00 3 /**< Bit for BG Tile Map Region Select */
257 #define LCDCF_B_OBJ16 2 /**< Bit for Sprites Size Select */
258 #define LCDCF_B_OBJON 1 /**< Bit for Sprites Display Visible/Hidden Select */
259 #define LCDCF_B_BGON 0 /**< Bit for Background Display Visible/Hidden Select */
260 #endif
261
262 __REG STAT_REG; /**< LCD status */
263 #define rSTAT STAT_REG
264
265 #if defined(__TARGET_ap)
266 #define STATF_LYC 0b00000010
267 #define STATF_MODE10 0b00000100
268 #define STATF_MODE01 0b00001000
269 #define STATF_MODE00 0b00010000
270 #define STATF_LYCF 0b00100000
271 #define STATF_HBL 0b00000000
272 #define STATF_VBL 0b10000000
273 #define STATF_OAM 0b01000000
274 #define STATF_LCD 0b11000000
275 #define STATF_BUSY 0b01000000
276 #define STATF_B_LYC 1
277 #define STATF_B_MODE10 2
278 #define STATF_B_MODE01 3
279 #define STATF_B_MODE00 4
280 #define STATF_B_LYCF 5
281 #define STATF_B_VBL 7
282 #define STATF_B_OAM 6
283 #define STATF_B_BUSY 6
284 #else
285 #define STATF_LYC 0b01000000 /**< STAT Interrupt: LYC=LY Coincidence Source Enable */
286 #define STATF_MODE10 0b00100000 /**< STAT Interrupt: Mode 2 OAM Source Enable */
287 #define STATF_MODE01 0b00010000 /**< STAT Interrupt: Mode 1 VBlank Source Enable */
288 #define STATF_MODE00 0b00001000 /**< STAT Interrupt: Mode 0 HBlank Source Enable */
289 #define STATF_LYCF 0b00000100 /**< LYC=LY Coincidence Status Flag, Set when LY contains the same value as LYC */
290 #define STATF_HBL 0b00000000 /**< Current LCD Mode is: 0, in H-Blank */
291 #define STATF_VBL 0b00000001 /**< Current LCD Mode is: 1, in V-Blank */
292 #define STATF_OAM 0b00000010 /**< Current LCD Mode is: 2, in OAM-RAM is used by system (Searching OAM) */
293 #define STATF_LCD 0b00000011 /**< Current LCD Mode is: 3, both OAM and VRAM used by system (Transferring Data to LCD Controller) */
294 #define STATF_BUSY 0b00000010 /**< When set, VRAM access is unsafe */
295 #define STATF_B_LYC 6 /**< Bit for STAT Interrupt: LYC=LY Coincidence Source Enable */
296 #define STATF_B_MODE10 5 /**< Bit for STAT Interrupt: Mode 2 OAM Source Enable */
297 #define STATF_B_MODE01 4 /**< Bit for STAT Interrupt: Mode 1 VBlank Source Enable */
298 #define STATF_B_MODE00 3 /**< Bit for STAT Interrupt: Mode 0 HBlank Source Enable */
299 #define STATF_B_LYCF 2 /**< Bit for LYC=LY Coincidence Status Flag */
300 #define STATF_B_VBL 0 /**< */
301 #define STATF_B_OAM 1 /**< */
302 #define STATF_B_BUSY 1 /**< Bit for when VRAM access is unsafe */
303 #endif
304
305 __REG SCY_REG; /**< Scroll Y */
306 #define rSCY
307 __REG SCX_REG; /**< Scroll X */
308 #define rSCX SCX_REG
309 __REG LY_REG; /**< LCDC Y-coordinate */
310 #define rLY LY_REG
311 __REG LYC_REG; /**< LY compare */
312 #define rLYC LYC_REG
313 __REG DMA_REG; /**< DMA transfer */
314 #define rDMA DMA_REG
315 __REG BGP_REG; /**< Set and Read the Background palette. \n \n Example with the DMG_PALETTE() helper function and constants: \n BGP_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE); */
316 #define rBGP BGP_REG
317 __REG OBP0_REG; /**< Set and Read the OBJ (Sprite) palette 0. \n \n The first color entry is always transparent. \n \n Example with the DMG_PALETTE() helper function and constants: \n OBP0_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE); */
318 #define rOBP0 OBP0_REG
319 __REG OBP1_REG; /**< Set and Read the OBJ (Sprite) palette 1. \n \n The first color entry is always transparent. \n \n Example with the DMG_PALETTE() helper function and constants: \n OBP1_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE); */
320 #define rOBP1 OBP1_REG
321 __REG WY_REG; /**< Window Y coordinate */
322 #define rWY WY_REG
323 __REG WX_REG; /**< Window X coordinate */
324 #define rWX WX_REG
325 __REG KEY1_REG; /**< CPU speed */
326 #define rKEY1 KEY1_REG
327 #define rSPD KEY1_REG
328
329 #define KEY1F_DBLSPEED 0b10000000
330 #define KEY1F_PREPARE 0b00000001
331
332 __REG VBK_REG; /**< VRAM bank select (CGB only) @see VBK_BANK_0, VBK_TILES, VBK_BANK_1, VBK_ATTRIBUTES */
333 #define rVBK VBK_REG
334
335 #define VBK_BANK_0 0 /**< Select Regular Map and Normal Tiles (CGB Mode Only) */
336 #define VBK_TILES 0 /**< Select Regular Map and Normal Tiles (CGB Mode Only) */
337 #define VBK_BANK_1 1 /**< Select Map Attributes and Extra Tile Bank (CGB Mode Only)*/
338 #define VBK_ATTRIBUTES 1 /**< Select Map Attributes and Extra Tile Bank (CGB Mode Only) */
339
340 #define BKGF_PRI 0b10000000 /**< Background CGB BG and Window over Sprite priority Enabled */
341 #define BKGF_YFLIP 0b01000000 /**< Background CGB Y axis flip: Vertically mirrored */
342 #define BKGF_XFLIP 0b00100000 /**< Background CGB X axis flip: Horizontally mirrored */
343 #define BKGF_BANK0 0b00000000 /**< Background CGB Tile VRAM-Bank: Use Bank 0 (CGB Mode Only) */
344 #define BKGF_BANK1 0b00001000 /**< Background CGB Tile VRAM-Bank: Use Bank 1 (CGB Mode Only) */
345
346 #define BKGF_CGB_PAL0 0b00000000 /**< Background CGB Palette number (CGB Mode Only) */
347 #define BKGF_CGB_PAL1 0b00000001 /**< Background CGB Palette number (CGB Mode Only) */
348 #define BKGF_CGB_PAL2 0b00000010 /**< Background CGB Palette number (CGB Mode Only) */
349 #define BKGF_CGB_PAL3 0b00000011 /**< Background CGB Palette number (CGB Mode Only) */
350 #define BKGF_CGB_PAL4 0b00000100 /**< Background CGB Palette number (CGB Mode Only) */
351 #define BKGF_CGB_PAL5 0b00000101 /**< Background CGB Palette number (CGB Mode Only) */
352 #define BKGF_CGB_PAL6 0b00000110 /**< Background CGB Palette number (CGB Mode Only) */
353 #define BKGF_CGB_PAL7 0b00000111 /**< Background CGB Palette number (CGB Mode Only) */
354
355 __REG HDMA1_REG; /**< DMA control 1 */
356 #define rHDMA1 HDMA1_REG
357 __REG HDMA2_REG; /**< DMA control 2 */
358 #define rHDMA2 HDMA2_REG
359 __REG HDMA3_REG; /**< DMA control 3 */
360 #define rHDMA3 HDMA3_REG
361 __REG HDMA4_REG; /**< DMA control 4 */
362 #define rHDMA4 HDMA4_REG
363 __REG HDMA5_REG; /**< DMA control 5 */
364 #define rHDMA5 HDMA5_REG
365
366 #define HDMA5F_MODE_GP 0b00000000
367 #define HDMA5F_MODE_HBL 0b10000000
368
369 #define HDMA5F_BUSY 0b10000000
370
371 __REG RP_REG; /**< IR port */
372 #define rRP RP_REG
373
374 #define RPF_ENREAD 0b11000000
375 #define RPF_DATAIN 0b00000010
376 #define RPF_WRITE_HI 0b00000001
377 #define RPF_WRITE_LO 0b00000000
378
379 __REG BCPS_REG; /**< BG color palette specification */
380 #define rBCPS BCPS_REG
381
382 #define BCPSF_AUTOINC 0b10000000
383 __REG BCPD_REG; /**< BG color palette data */
384 #define rBCPD BCPD_REG
385
386 __REG OCPS_REG; /**< OBJ color palette specification */
387 #define rOCPS OCPS_REG
388
389 #define OCPSF_AUTOINC 0b10000000
390 __REG OCPD_REG; /**< OBJ color palette data */
391 #define rOCPD OCPD_REG
392 __REG SVBK_REG; /**< Selects the WRAM upper region bank (CGB Only). WRAM Banking is NOT officially supported in GBDK and SDCC. The stack must be moved and other special care taken. */
393 #define rSVBK SVBK_REG
394 #define rSMBK SVBK_REG
395
396 __REG PCM12_REG; /**< Sound channel 1&2 PCM amplitude (R) */
397 #define rPCM12 PCM12_REG
398
399 __REG PCM34_REG; /**< Sound channel 3&4 PCM amplitude (R) */
400 #define rPCM34 PCM34_REG
401
402 __REG IE_REG; /**< Interrupt enable */
403 #define rIE IE_REG
404
405 #define IEF_HILO 0b00010000 /**< Joypad interrupt enable flag */
406 #define IEF_SERIAL 0b00001000 /**< Serial interrupt enable flag */
407 #define IEF_TIMER 0b00000100 /**< Timer interrupt enable flag */
408 #define IEF_STAT 0b00000010 /**< Stat interrupt enable flag */
409 #define IEF_VBLANK 0b00000001 /**< VBlank interrupt enable flag */
410
411
412 /* Square wave duty cycle */
413 #define AUDLEN_DUTY_12_5 0b00000000
414 #define AUDLEN_DUTY_25 0b01000000
415 #define AUDLEN_DUTY_50 0b10000000
416 #define AUDLEN_DUTY_75 0b11000000
417 #define AUDLEN_LENGTH(x) (x)
418
419 /* Audio envelope flags */
420 #define AUDENV_VOL(x) ((x) << 4)
421 #define AUDENV_UP 0b00001000
422 #define AUDENV_DOWN 0b00000000
423 #define AUDENV_LENGTH(x) (x)
424
425 /* Audio trigger flags */
426 #define AUDHIGH_RESTART 0b10000000
427 #define AUDHIGH_LENGTH_ON 0b01000000
428 #define AUDHIGH_LENGTH_OFF 0b00000000
429
430 /* OAM attributes flags */
431 #define OAMF_PRI 0b10000000 /**< BG and Window over Sprite Enabled */
432 #define OAMF_YFLIP 0b01000000 /**< Sprite Y axis flip: Vertically mirrored */
433 #define OAMF_XFLIP 0b00100000 /**< Sprite X axis flip: Horizontally mirrored */
434 #define OAMF_PAL0 0b00000000 /**< Sprite Palette number: use OBP0 (Non-CGB Mode Only) */
435 #define OAMF_PAL1 0b00010000 /**< Sprite Palette number: use OBP1 (Non-CGB Mode Only) */
436 #define OAMF_BANK0 0b00000000 /**< Sprite Tile VRAM-Bank: Use Bank 0 (CGB Mode Only) */
437 #define OAMF_BANK1 0b00001000 /**< Sprite Tile VRAM-Bank: Use Bank 1 (CGB Mode Only) */
438
439 #define OAMF_CGB_PAL0 0b00000000 /**< Sprite CGB Palette number: use OCP0 (CGB Mode Only) */
440 #define OAMF_CGB_PAL1 0b00000001 /**< Sprite CGB Palette number: use OCP1 (CGB Mode Only) */
441 #define OAMF_CGB_PAL2 0b00000010 /**< Sprite CGB Palette number: use OCP2 (CGB Mode Only) */
442 #define OAMF_CGB_PAL3 0b00000011 /**< Sprite CGB Palette number: use OCP3 (CGB Mode Only) */
443 #define OAMF_CGB_PAL4 0b00000100 /**< Sprite CGB Palette number: use OCP4 (CGB Mode Only) */
444 #define OAMF_CGB_PAL5 0b00000101 /**< Sprite CGB Palette number: use OCP5 (CGB Mode Only) */
445 #define OAMF_CGB_PAL6 0b00000110 /**< Sprite CGB Palette number: use OCP6 (CGB Mode Only) */
446 #define OAMF_CGB_PAL7 0b00000111 /**< Sprite CGB Palette number: use OCP7 (CGB Mode Only) */
447
448 #define OAMF_PALMASK 0b00000111 /**< Mask for Sprite CGB Palette number (CGB Mode Only) */
449
450 #define DEVICE_SCREEN_X_OFFSET 0 /**< Offset of visible screen (in tile units) from left edge of hardware map */
451 #define DEVICE_SCREEN_Y_OFFSET 0 /**< Offset of visible screen (in tile units) from top edge of hardware map */
452 #define DEVICE_SCREEN_WIDTH 20 /**< Width of visible screen in tile units */
453 #define DEVICE_SCREEN_HEIGHT 18 /**< Height of visible screen in tile units */
454 #define DEVICE_SCREEN_BUFFER_WIDTH 32 /**< Width of hardware map buffer in tile units */
455 #define DEVICE_SCREEN_BUFFER_HEIGHT 32 /**< Height of hardware map buffer in tile units */
456 #define DEVICE_SCREEN_MAP_ENTRY_SIZE 1 /**< Number of bytes per hardware map entry */
457 #define DEVICE_SPRITE_PX_OFFSET_X 8 /**< Offset of sprite X coordinate origin (in pixels) from left edge of visible screen */
458 #define DEVICE_SPRITE_PX_OFFSET_Y 16 /**< Offset of sprite Y coordinate origin (in pixels) from top edge of visible screen */
459 #define DEVICE_WINDOW_PX_OFFSET_X 7 /**< Minimal X coordinate of the window layer */
460 #define DEVICE_WINDOW_PX_OFFSET_Y 0 /**< Minimal Y coordinate of the window layer */
461 #define DEVICE_SCREEN_PX_WIDTH (DEVICE_SCREEN_WIDTH * 8) /**< Width of visible screen in pixels */
462 #define DEVICE_SCREEN_PX_HEIGHT (DEVICE_SCREEN_HEIGHT * 8) /**< Height of visible screen in pixels */
463
464 typedef UINT8 scroll_x_t;
465 typedef UINT8 scroll_y_t;
466 #endif
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