gbdk-2020 | GameBoy Development Kit |
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gbdk-lib/include/sms/hardware.h
1 /** @file sms/hardware.h
2 Defines that let the SMS/GG hardware registers be accessed
3 from C.
4 */
5 #ifndef _HARDWARE_H
6 #define _HARDWARE_H
7
8 #include <types.h>
9
10 #define __BYTES extern UBYTE
11 #define __BYTE_REG extern volatile UBYTE
12
13 static volatile SFR AT(0x00) GG_STATE; /**< Game Gear status register for Start/Pause, Japan vs Overseas mode (NJAP), NTSC/PAL mode */
14
15 #define GGSTATE_STT 0b10000000
16 #define GGSTATE_NJAP 0b01000000
17 #define GGSTATE_NNTS 0b00100000
18
19 static volatile SFR AT(0x01) GG_EXT_7BIT; /**< Game Gear Serial port register used to read/write data when the EXT connector used as 7-bit input/output port */
20
21 static volatile SFR AT(0x02) GG_EXT_CTL; /**< Game Gear Serial port register for configuring external NMI */
22
23 #define GGEXT_NINT 0b10000000
24
25 static volatile SFR AT(0x03) GG_SIO_SEND; /**< Game Gear Serial Data Send register */
26 static volatile SFR AT(0x04) GG_SIO_RECV; /**< Game Gear Serial Data Receive register */
27 static volatile SFR AT(0x05) GG_SIO_CTL; /**< Game Gear Serial Port control register */
28
29 #define SIOCTL_TXFL 0b00000001
30 #define SIOCTL_RXRD 0b00000010
31 #define SIOCTL_FRER 0b00000100
32 #define SIOCTL_INT 0b00001000
33 #define SIOCTL_TON 0b00010000
34 #define SIOCTL_RON 0b00100000
35 #define SIOCTL_BS0 0b01000000
36 #define SIOCTL_BS1 0b10000000
37
38 static volatile SFR AT(0x06) GG_SOUND_PAN; /**< Game Gear Sound panning (left / right) register */
39
40 #define SOUNDPAN_TN1R 0b00000001
41 #define SOUNDPAN_TN2R 0b00000010
42 #define SOUNDPAN_TN3R 0b00000100
43 #define SOUNDPAN_NOSR 0b00001000
44 #define SOUNDPAN_TN1L 0b00010000
45 #define SOUNDPAN_TN2L 0b00100000
46 #define SOUNDPAN_TN3L 0b01000000
47 #define SOUNDPAN_NOSL 0b10000000
48
49 static volatile SFR AT(0x3E) MEMORY_CTL;
50
51 #define MEMCTL_JOYON 0b00000000
52 #define MEMCTL_JOYOFF 0b00000100
53 #define MEMCTL_BASEON 0b00000000
54 #define MEMCTL_BASEOFF 0b00001000
55 #define MEMCTL_RAMON 0b00000000
56 #define MEMCTL_RAMOFF 0b00010000
57 #define MEMCTL_CROMON 0b00000000
58 #define MEMCTL_CROMOFF 0b00100000
59 #define MEMCTL_ROMON 0b00000000
60 #define MEMCTL_ROMOFF 0b01000000
61 #define MEMCTL_EXTON 0b00000000
62 #define MEMCTL_EXTOFF 0b10000000
63
64 static volatile SFR AT(0x3F) JOY_CTL;
65
66 #define JOY_P1_TR_DIR_IN 0b00000001
67 #define JOY_P1_TR_DIR_OUT 0b00000000
68 #define JOY_P1_TH_DIR_IN 0b00000010
69 #define GUN_P1_LATCH JOY_P1_TH_DIR_IN
70 #define JOY_P1_TH_DIR_OUT 0b00000000
71 #define JOY_P2_TR_DIR_IN 0b00000100
72 #define JOY_P2_TR_DIR_OUT 0b00000000
73 #define JOY_P2_TH_DIR_IN 0b00001000
74 #define GUN_P2_LATCH JOY_P2_TH_DIR_IN
75 #define JOY_P2_TH_DIR_OUT 0b00000000
76 #define JOY_P1_TR_OUT_HI 0b00010000
77 #define JOY_P1_TR_OUT_LO 0b00000000
78 #define JOY_P1_TH_OUT_HI 0b00100000
79 #define JOY_P1_TH_OUT_LO 0b00000000
80 #define JOY_P2_TR_OUT_HI 0b01000000
81 #define JOY_P2_TR_OUT_LO 0b00000000
82 #define JOY_P2_TH_OUT_HI 0b10000000
83 #define JOY_P2_TH_OUT_LO 0b00000000
84
85 #define JOY_TH_HI (JOY_P1_TR_DIR_IN | JOY_P1_TH_DIR_OUT | JOY_P2_TR_DIR_IN | JOY_P2_TH_DIR_OUT | JOY_P1_TR_OUT_HI | JOY_P1_TH_OUT_HI | JOY_P2_TR_OUT_HI | JOY_P2_TH_OUT_HI)
86 #define JOY_TH_LO (JOY_P1_TR_DIR_IN | JOY_P1_TH_DIR_OUT | JOY_P2_TR_DIR_IN | JOY_P2_TH_DIR_OUT | JOY_P1_TR_OUT_HI | JOY_P1_TH_OUT_LO | JOY_P2_TR_OUT_HI | JOY_P2_TH_OUT_LO)
87
88 static volatile SFR AT(0x7E) VCOUNTER;
89
90 static volatile SFR AT(0x7F) PSG;
91
92 #define PSG_LATCH 0b10000000
93
94 #define PSG_CH0 0b00000000
95 #define PSG_CH1 0b00100000
96 #define PSG_CH2 0b01000000
97 #define PSG_CH3 0b01100000
98
99 #define PSG_VOLUME 0b00010000
100
101 static volatile SFR AT(0x7F) HCOUNTER;
102
103 static volatile SFR AT(0xBE) VDP_DATA;
104 static volatile SFR AT(0xBF) VDP_CMD;
105 static volatile SFR AT(0xBF) VDP_STATUS;
106
107 #define STATF_INT_VBL 0b10000000
108 #define STATF_9_SPR 0b01000000
109 #define STATF_SPR_COLL 0b00100000
110
111 #define VDP_REG_MASK 0b10000000
112 #define VDP_R0 0b10000000
113 extern UBYTE shadow_VDP_R0;
114
115 #define R0_VSCRL 0b00000000
116 #define R0_VSCRL_INH 0b10000000
117 #define R0_HSCRL 0b00000000
118 #define R0_HSCRL_INH 0b01000000
119 #define R0_NO_LCB 0b00000000
120 #define R0_LCB 0b00100000
121 #define R0_IE1_OFF 0b00000000
122 #define R0_IE1 0b00010000
123 #define R0_SS_OFF 0b00000000
124 #define R0_SS 0b00001000
125 #define R0_DEFAULT 0b00000110
126 #define R0_ES_OFF 0b00000000
127 #define R0_ES 0b00000001
128
129 #define VDP_R1 0b10000001
130 extern UBYTE shadow_VDP_R1;
131
132 #define R1_DEFAULT 0b10000000
133 #define R1_DISP_OFF 0b00000000
134 #define R1_DISP_ON 0b01000000
135 #define R1_IE_OFF 0b00000000
136 #define R1_IE 0b00100000
137 #define R1_SPR_8X8 0b00000000
138 #define R1_SPR_8X16 0b00000010
139
140 #define VDP_R2 0b10000010
141 extern UBYTE shadow_VDP_R2;
142
143 #define R2_MAP_0x3800 0xFF
144 #define R2_MAP_0x3000 0xFD
145 #define R2_MAP_0x2800 0xFB
146 #define R2_MAP_0x2000 0xF9
147 #define R2_MAP_0x1800 0xF7
148 #define R2_MAP_0x1000 0xF5
149 #define R2_MAP_0x0800 0xF3
150 #define R2_MAP_0x0000 0xF1
151
152 #define VDP_R3 0b10000011
153 extern UBYTE shadow_VDP_R3;
154 #define VDP_R4 0b10000100
155 extern UBYTE shadow_VDP_R4;
156 #define VDP_R5 0b10000101
157 extern UBYTE shadow_VDP_R5;
158
159 #define R5_SAT_0x3F00 0xFF
160 #define R5_SAT_0x1F00 0xBF
161 #define R5_SAT_MASK 0b10000001
162
163 #define VDP_R6 0b10000110
164 extern UBYTE shadow_VDP_R6;
165
166 #define R6_BANK0 0xFB
167 #define R6_DATA_0x0000 0xFB
168 #define R6_BANK1 0xFF
169 #define R6_DATA_0x2000 0xFF
170
171 #define VDP_R7 0b10000111
172 extern UBYTE shadow_VDP_R7;
173 #define VDP_RBORDER 0b10000111
174 extern UBYTE shadow_VDP_RBORDER;
175
176 #define R7_COLOR_MASK 0b11110000
177
178 #define VDP_R8 0b10001000
179 extern UBYTE shadow_VDP_R8;
180 #define VDP_RSCX 0b10001000
181 extern UBYTE shadow_VDP_RSCX;
182
183 #define VDP_R9 0b10001001
184 extern UBYTE shadow_VDP_R9;
185 #define VDP_RSCY 0b10001001
186 extern UBYTE shadow_VDP_RSCY;
187
188 #define VDP_R10 0b10001010
189 extern UBYTE shadow_VDP_R10;
190
191 #define R10_INT_OFF 0xFF
192 #define R10_INT_EVERY 0x00
193
194 static volatile SFR AT(0xDC) JOY_PORT1;
195
196 #define JOY_P1_UP 0b00000001
197 #define JOY_P1_MD_Z JOY_P1_UP
198 #define JOY_P1_DOWN 0b00000010
199 #define JOY_P1_MD_Y JOY_P1_DOWN
200 #define JOY_P1_LEFT 0b00000100
201 #define JOY_P1_MD_X JOY_P1_LEFT
202 #define JOY_P1_RIGHT 0b00001000
203 #define JOY_P1_MD_MODE JOY_P1_RIGHT
204 #define JOY_P1_SW1 0b00010000
205 #define JOY_P1_TRIGGER JOY_P1_SW1
206 #define JOY_P1_MD_A JOY_P1_SW1
207 #define JOY_P1_SW2 0b00100000
208 #define JOY_P1_MD_START JOY_P1_SW2
209 #define JOY_P2_UP 0b01000000
210 #define JOY_P2_MD_Z JOY_P2_UP
211 #define JOY_P2_DOWN 0b10000000
212 #define JOY_P2_MD_Y JOY_P2_DOWN
213
214 static volatile SFR AT(0xDD) JOY_PORT2;
215
216 #define JOY_P2_LEFT 0b00000001
217 #define JOY_P2_MD_X JOY_P2_LEFT
218 #define JOY_P2_RIGHT 0b00000010
219 #define JOY_P2_MD_MODE JOY_P2_RIGHT
220 #define JOY_P2_SW1 0b00000100
221 #define JOY_P2_TRIGGER JOY_P2_SW1
222 #define JOY_P2_MD_A JOY_P2_SW1
223 #define JOY_P2_SW2 0b00001000
224 #define JOY_P2_MD_START JOY_P2_SW2
225 #define JOY_RESET 0b00010000
226 #define JOY_P1_LIGHT 0b01000000
227 #define JOY_P2_LIGHT 0b10000000
228
229 static volatile SFR AT(0xF0) FMADDRESS;
230 static volatile SFR AT(0xF1) FMDATA;
231 static volatile SFR AT(0xF2) AUDIOCTRL;
232
233 static volatile UBYTE AT(0xfffc) RAM_CONTROL;
234
235 #define RAMCTL_BANK 0b00000100
236 #define RAMCTL_ROM 0b00000000
237 #define RAMCTL_RAM 0b00001000
238 #define RAMCTL_RO 0b00010000
239 #define RAMCTL_PROT 0b10000000
240
241 static volatile UBYTE AT(0xfff8) GLASSES_3D;
242
243 static volatile UBYTE AT(0xfffd) MAP_FRAME0;
244 static volatile UBYTE AT(0xfffe) MAP_FRAME1;
245 static volatile UBYTE AT(0xffff) MAP_FRAME2;
246
247 extern volatile UBYTE TIMA_REG;
248 extern volatile UBYTE TMA_REG;
249 extern volatile UBYTE TAC_REG;
250
251 extern volatile UBYTE VDP_ATTR_SHIFT;
252
253 #define VBK_TILES 0
254 #define VBK_ATTRIBUTES 1
255
256 #define VDP_SAT_TERM 0xD0
257
258 #if defined(__TARGET_sms)
259 #define DEVICE_SCREEN_X_OFFSET 0
260 #define DEVICE_SCREEN_Y_OFFSET 0
261 #define DEVICE_SCREEN_WIDTH 32
262 #define DEVICE_SCREEN_HEIGHT 24
263 #define DEVICE_SCREEN_BUFFER_WIDTH 32
264 #define DEVICE_SCREEN_BUFFER_HEIGHT 28
265 #define DEVICE_SCREEN_MAP_ENTRY_SIZE 2
266 #define DEVICE_SPRITE_PX_OFFSET_X 0
267 #define DEVICE_SPRITE_PX_OFFSET_Y -1
268 #define DEVICE_WINDOW_PX_OFFSET_X 0
269 #define DEVICE_WINDOW_PX_OFFSET_Y 0
270 #elif defined(__TARGET_gg)
271 #define DEVICE_SCREEN_X_OFFSET 6
272 #define DEVICE_SCREEN_Y_OFFSET 3
273 #define DEVICE_SCREEN_WIDTH 20
274 #define DEVICE_SCREEN_HEIGHT 18
275 #define DEVICE_SCREEN_BUFFER_WIDTH 32
276 #define DEVICE_SCREEN_BUFFER_HEIGHT 28
277 #define DEVICE_SCREEN_MAP_ENTRY_SIZE 2
278 #define DEVICE_SPRITE_PX_OFFSET_X 48
279 #define DEVICE_SPRITE_PX_OFFSET_Y 23
280 #define DEVICE_WINDOW_PX_OFFSET_X 0
281 #define DEVICE_WINDOW_PX_OFFSET_Y 0
282 #else
283 #error Unrecognized port
284 #endif
285 #define DEVICE_SCREEN_PX_WIDTH (DEVICE_SCREEN_WIDTH * 8)
286 #define DEVICE_SCREEN_PX_HEIGHT (DEVICE_SCREEN_HEIGHT * 8)
287
288 typedef UINT8 scroll_x_t;
289 typedef UINT8 scroll_y_t;
290 #endif
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