git.y1.nz

commit 7a3ebb708c528f3e1c069f03bc1a185b1b02744b
parent db483ce95f31655fec74ddc53495d78f33903c77
Author: Lior Halphon <LIJI32@gmail.com>
Date:   Sat, 12 Dec 2020 22:55:14 +0200

LCDC write timing regression fix

Diffstat:
M
Core/sm83_cpu.c
2
++

1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/Core/sm83_cpu.c b/Core/sm83_cpu.c
@@ -249,6 +249,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
                 // Todo: This is difference is because my timing is off in one of the models
                 if (gb->model > GB_MODEL_CGB_C) {
                     GB_advance_cycles(gb, gb->pending_cycles);
+                    GB_write_memory(gb, addr, value ^ 0x10); // Write with the old TILE_SET first
                     gb->tile_sel_glitch = true;
                     GB_advance_cycles(gb, 1);
                     gb->tile_sel_glitch = false;
@@ -257,6 +258,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
                 }
                 else {
                     GB_advance_cycles(gb, gb->pending_cycles - 1);
+                    GB_write_memory(gb, addr, value ^ 0x10); // Write with the old TILE_SET first
                     gb->tile_sel_glitch = true;
                     GB_advance_cycles(gb, 1);
                     gb->tile_sel_glitch = false;

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