git.y1.nz

commit 9b5dc9eca796bf6f10b0da2e34837e84b44646be
parent b932f6699e0e3a61f6a9fdab0354f4c51251b64b
Author: Lior Halphon <LIJI32@gmail.com>
Date:   Sun, 12 Jun 2022 21:43:04 +0300

Refine TILE_SEL glitch, fixes #445

Diffstat:
M
Core/sm83_cpu.c
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Core/sm83_cpu.c b/Core/sm83_cpu.c
@@ -242,7 +242,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
             break;
             
         case GB_CONFLICT_CGB_LCDC:
-            if ((value ^ gb->io_registers[GB_IO_LCDC]) & 0x10) {
+            if ((~value & gb->io_registers[GB_IO_LCDC]) & 0x10) {
                 // Todo: This is difference is because my timing is off in one of the models
                 if (gb->model > GB_MODEL_CGB_C) {
                     GB_advance_cycles(gb, gb->pending_cycles);

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