gbdk-2020 | GameBoy Development Kit |
| download: https://git.y1.nz/archives/gbdk.tar.gz | |
| README | Files | Log | Refs | LICENSE |
commit 818d037217382fdd8d19d62e05242cec74ae0cf5 parent 593b4cfc996fdb28ea4d9b42b3ea9e9d509528fc Author: Toxa <untoxa@mail.ru> Date: Tue, 13 Jul 2021 00:33:02 +0300 a bit of constants Diffstat:
| M | gbdk-lib/include/gb/hardware.h | 307 | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------- |
| M | gbdk-lib/libc/gb/sfr.s | 114 | ++++++++++++++++++++++++++++++++++++++++++------------------------------------- |
2 files changed, 310 insertions(+), 111 deletions(-)
diff --git a/gbdk-lib/include/gb/hardware.h b/gbdk-lib/include/gb/hardware.h @@ -11,60 +11,253 @@ #define __REG extern volatile __sfr -__REG P1_REG ; /**< Joystick: 1.1.P15.P14.P13.P12.P11.P10 */ -__REG SB_REG ; /**< Serial IO data buffer */ -__REG SC_REG ; /**< Serial IO control register */ -__REG DIV_REG ; /**< Divider register */ -__REG TIMA_REG ; /**< Timer counter */ -__REG TMA_REG ; /**< Timer modulo */ -__REG TAC_REG ; /**< Timer control */ -__REG IF_REG ; /**< Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL */ -__REG NR10_REG ; /**< Sound Channel 1 Sweep */ -__REG NR11_REG ; /**< Sound Channel 1 Sound length/Wave pattern duty */ -__REG NR12_REG ; /**< Sound Channel 1 Volume Envelope */ -__REG NR13_REG ; /**< Sound Channel 1 Frequency Low */ -__REG NR14_REG ; /**< Sound Channel 1 Frequency High */ -__REG NR21_REG ; /**< Sound Channel 2 Tone */ -__REG NR22_REG ; /**< Sound Channel 2 Volume Envelope */ -__REG NR23_REG ; /**< Sound Channel 2 Frequency data Low */ -__REG NR24_REG ; /**< Sound Channel 2 Frequency data High */ -__REG NR30_REG ; /**< Sound Channel 3 Sound on/off */ -__REG NR31_REG ; /**< Sound Channel 3 Sound Length */ -__REG NR32_REG ; /**< Sound Channel 3 Select output level */ -__REG NR33_REG ; /**< Sound Channel 3 Frequency data Low */ -__REG NR34_REG ; /**< Sound Channel 3 Frequency data High */ -__REG NR41_REG ; /**< Sound Channel 4 Sound Length */ -__REG NR42_REG ; /**< Sound Channel 4 Volume Envelope */ -__REG NR43_REG ; /**< Sound Channel 4 Polynomial Counter */ -__REG NR44_REG ; /**< Sound Channel 4 Counter / Consecutive and Inital */ -__REG NR50_REG ; /**< Sound Channel control / ON-OFF / Volume */ -__REG NR51_REG ; /**< Sound Selection of Sound output terminal */ -__REG NR52_REG ; /**< Sound Master on/off */ -__REG LCDC_REG ; /**< LCD control */ -__REG STAT_REG ; /**< LCD status */ -__REG SCY_REG ; /**< Scroll Y */ -__REG SCX_REG ; /**< Scroll X */ -__REG LY_REG ; /**< LCDC Y-coordinate */ -__REG LYC_REG ; /**< LY compare */ -__REG DMA_REG ; /**< DMA transfer */ -__REG BGP_REG ; /**< BG palette data */ -__REG OBP0_REG ; /**< OBJ palette 0 data */ -__REG OBP1_REG ; /**< OBJ palette 1 data */ -__REG WY_REG ; /**< Window Y coordinate */ -__REG WX_REG ; /**< Window X coordinate */ -__REG KEY1_REG ; /**< CPU speed */ -__REG VBK_REG ; /**< VRAM bank */ -__REG HDMA1_REG ; /**< DMA control 1 */ -__REG HDMA2_REG ; /**< DMA control 2 */ -__REG HDMA3_REG ; /**< DMA control 3 */ -__REG HDMA4_REG ; /**< DMA control 4 */ -__REG HDMA5_REG ; /**< DMA control 5 */ -__REG RP_REG ; /**< IR port */ -__REG BCPS_REG ; /**< BG color palette specification */ -__REG BCPD_REG ; /**< BG color palette data */ -__REG OCPS_REG ; /**< OBJ color palette specification */ -__REG OCPD_REG ; /**< OBJ color palette data */ -__REG SVBK_REG ; /**< WRAM bank */ -__REG IE_REG ; /**< Interrupt enable */ - -#endif /* _HARDWARE_H */ +__REG P1_REG; /** Joystick: 1.1.P15.P14.P13.P12.P11.P10 */ +#define rP1 P1_REG + +#define P1F_5 0b00100000u +#define P1F_4 0b00010000u +#define P1F_3 0b00001000u +#define P1F_2 0b00000100u +#define P1F_1 0b00000010u +#define P1F_0 0b00000001u + +#define P1F_GET_DPAD P1F_5 +#define P1F_GET_BTN P1F_4 +#define P1F_GET_NONE (P1F_4 | P1F_5) + +__REG SB_REG; /** Serial IO data buffer */ +#define rSB SB_REG +__REG SC_REG; /** Serial IO control register */ +#define rSC SC_REG +__REG DIV_REG; /** Divider register */ +#define rDIV DIV_REG +__REG TIMA_REG; /** Timer counter */ +#define rTIMA TIMA_REG +__REG TMA_REG; /** Timer modulo */ +#define rTMA TMA_REG +__REG TAC_REG; /** Timer control */ +#define rTAC TAC_REG + +#define TACF_START 0b00000100u +#define TACF_STOP 0b00000000u +#define TACF_4KHZ 0b00000000u +#define TACF_16KHZ 0b00000011u +#define TACF_65KHZ 0b00000010u +#define TACF_262KHZ 0b00000001u + +__REG IF_REG; /** Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL */ +#define rIF IF_REG + +__REG NR10_REG; /** Sound Channel 1 Sweep */ +#define rAUD1SWEEP NR10_REG +#define AUD1SWEEP_UP 0b00000000u +#define AUD1SWEEP_DOWN 0b00001000u +__REG NR11_REG; /** Sound Channel 1 Sound length/Wave pattern duty */ +#define rAUD1LEN NR11_REG +__REG NR12_REG; /** Sound Channel 1 Volume Envelope */ +#define rAUD1ENV NR12_REG +__REG NR13_REG; /** Sound Channel 1 Frequency Low */ +#define rAUD1LOW NR13_REG +__REG NR14_REG; /** Sound Channel 1 Frequency High */ +#define rAUD1HIGH NR14_REG + +__REG NR21_REG; /** Sound Channel 2 Tone */ +#define rAUD2LEN NR21_REG +__REG NR22_REG; /** Sound Channel 2 Volume Envelope */ +#define rAUD2ENV NR22_REG +__REG NR23_REG; /** Sound Channel 2 Frequency data Low */ +#define rAUD2LOW NR23_REG +__REG NR24_REG; /** Sound Channel 2 Frequency data High */ +#define rAUD2HIGH NR24_REG + +__REG NR30_REG; /** Sound Channel 3 Sound on/off */ +#define rAUD3ENA NR30_REG +__REG NR31_REG; /** Sound Channel 3 Sound Length */ +#define rAUD3LEN NR31_REG +__REG NR32_REG; /** Sound Channel 3 Select output level */ +#define rAUD3LEVEL NR32_REG +__REG NR33_REG; /** Sound Channel 3 Frequency data Low */ +#define rAUD3LOW NR33_REG +__REG NR34_REG; /** Sound Channel 3 Frequency data High */ +#define rAUD3HIGH NR34_REG + +__REG NR41_REG; /** Sound Channel 4 Sound Length */ +#define rAUD4LEN NR41_REG +__REG NR42_REG; /** Sound Channel 4 Volume Envelope */ +#define rAUD4ENV NR42_REG +__REG NR43_REG; /** Sound Channel 4 Polynomial Counter */ +#define rAUD4POLY NR43_REG +__REG NR44_REG; /** Sound Channel 4 Counter / Consecutive and Inital */ +#define rAUD4GO NR44_REG + +__REG NR50_REG; /** Sound Channel control / ON-OFF / Volume */ +#define rAUDVOL NR50_REG + +#define AUDVOL_VIN_LEFT 0b10000000u +#define AUDVOL_VIN_RIGHT 0b00001000u + +__REG NR51_REG; /** Sound Selection of Sound output terminal */ +#define rAUDTERM NR51_REG + +#define AUDTERM_4_LEFT 0b10000000u +#define AUDTERM_3_LEFT 0b01000000u +#define AUDTERM_2_LEFT 0b00100000u +#define AUDTERM_1_LEFT 0b00010000u +#define AUDTERM_4_RIGHT 0b00001000u +#define AUDTERM_3_RIGHT 0b00000100u +#define AUDTERM_2_RIGHT 0b00000010u +#define AUDTERM_1_RIGHT 0b00000001u + +__REG NR52_REG; /** Sound Master on/off */ +#define rAUDENA NR52_REG + +#define AUDENA_ON 0b10000000u +#define AUDENA_OFF 0b00000000u + +__REG LCDC_REG; /** LCD control */ +#define rLCDC LCDC_REG + +#define LCDCF_OFF 0b00000000u +#define LCDCF_ON 0b10000000u +#define LCDCF_WIN9800 0b00000000u +#define LCDCF_WIN9C00 0b01000000u +#define LCDCF_WINOFF 0b00000000u +#define LCDCF_WINON 0b00100000u +#define LCDCF_BG8800 0b00000000u +#define LCDCF_BG8000 0b00010000u +#define LCDCF_BG9800 0b00000000u +#define LCDCF_BG9C00 0b00001000u +#define LCDCF_OBJ8 0b00000000u +#define LCDCF_OBJ16 0b00000100u +#define LCDCF_OBJOFF 0b00000000u +#define LCDCF_OBJON 0b00000010u +#define LCDCF_BGOFF 0b00000000u +#define LCDCF_BGON 0b00000001u + +__REG STAT_REG; /** LCD status */ +#define rSTAT STAT_REG + +#define STATF_LYC 0b01000000u +#define STATF_MODE10 0b00100000u +#define STATF_MODE01 0b00010000u +#define STATF_MODE00 0b00001000u +#define STATF_LYCF 0b00000100u +#define STATF_HBL 0b00000000u +#define STATF_VBL 0b00000001u +#define STATF_OAM 0b00000010u +#define STATF_LCD 0b00000011u +#define STATF_BUSY 0b00000010u + +__REG SCY_REG; /** Scroll Y */ +#define rSCY +__REG SCX_REG; /** Scroll X */ +#define rSCX SCX_REG +__REG LY_REG; /** LCDC Y-coordinate */ +#define rLY LY_REG +__REG LYC_REG; /** LY compare */ +#define rLYC LYC_REG +__REG DMA_REG; /** DMA transfer */ +#define rDMA DMA_REG +__REG BGP_REG; /** BG palette data */ +#define rBGP BGP_REG +__REG OBP0_REG; /** OBJ palette 0 data */ +#define rOBP0 OBP0_REG +__REG OBP1_REG; /** OBJ palette 1 data */ +#define rOBP1 OBP1_REG +__REG WY_REG; /** Window Y coordinate */ +#define rWY WY_REG +__REG WX_REG; /** Window X coordinate */ +#define rWX WX_REG +__REG KEY1_REG; /** CPU speed */ +#define rKEY1 KEY1_REG +#define rSPD KEY1_REG + +#define KEY1F_DBLSPEED 0b10000000u +#define KEY1F_PREPARE 0b00000001u + +__REG VBK_REG; /** VRAM bank */ +#define rVBK VBK_REG +__REG HDMA1_REG; /** DMA control 1 */ +#define rHDMA1 HDMA1_REG +__REG HDMA2_REG; /** DMA control 2 */ +#define rHDMA2 HDMA2_REG +__REG HDMA3_REG; /** DMA control 3 */ +#define rHDMA3 HDMA3_REG +__REG HDMA4_REG; /** DMA control 4 */ +#define rHDMA4 HDMA4_REG +__REG HDMA5_REG; /** DMA control 5 */ +#define rHDMA5 HDMA5_REG + +#define HDMA5F_MODE_GP 0b00000000u +#define HDMA5F_MODE_HBL 0b10000000u + +#define HDMA5F_BUSY 0b10000000u + +__REG RP_REG; /** IR port */ +#define rRP RP_REG + +#define RPF_ENREAD 0b11000000u +#define RPF_DATAIN 0b00000010u +#define RPF_WRITE_HI 0b00000001u +#define RPF_WRITE_LO 0b00000000u + +__REG BCPS_REG; /** BG color palette specification */ +#define rBCPS BCPS_REG + +#define BCPSF_AUTOINC 0b10000000u +__REG BCPD_REG; /** BG color palette data */ +#define rBCPD BCPD_REG +__REG OCPS_REG; /** OBJ color palette specification */ +#define rOCPS OCPS_REG + +#define OCPSF_AUTOINC 0b10000000u +__REG OCPD_REG; /** OBJ color palette data */ +#define rOCPD OCPD_REG +__REG SVBK_REG; /** WRAM bank */ +#define rSVBK SVBK_REG +#define rSMBK SVBK_REG + +__REG PCM12_REG; /** Sound channel 1&2 PCM amplitude (R) */ +#define rPCM12 PCM12_REG + +__REG PCM34_REG; /** Sound channel 3&4 PCM amplitude (R) */ +#define rPCM34 PCM34_REG + +__REG IE_REG; /** Interrupt enable */ +#define rIE IE_REG + +#define IEF_HILO 0b00010000u +#define IEF_SERIAL 0b00001000u +#define IEF_TIMER 0b00000100u +#define IEF_STAT 0b00000010u +#define IEF_VBLANK 0b00000001u + + +/* Square wave duty cycle */ +#define AUDLEN_DUTY_12_5 0b00000000u +#define AUDLEN_DUTY_25 0b01000000u +#define AUDLEN_DUTY_50 0b10000000u +#define AUDLEN_DUTY_75 0b11000000u + + +/* Audio envelope flags */ +#define AUDENV_UP 0b00001000u +#define AUDENV_DOWN 0b00000000u + +/* Audio trigger flags */ +#define AUDHIGH_RESTART 0b10000000u +#define AUDHIGH_LENGTH_ON 0b01000000u +#define AUDHIGH_LENGTH_OFF 0b00000000u + +/* OAM attributes flags */ +#define OAMF_PRI 0b10000000u +#define OAMF_YFLIP 0b01000000u +#define OAMF_XFLIP 0b00100000u +#define OAMF_PAL0 0b00000000u +#define OAMF_PAL1 0b00010000u +#define OAMF_BANK0 0b00000000u +#define OAMF_BANK1 0b00001000u + +#define OAMF_PALMASK 0b00000111u + +#endif diff --git a/gbdk-lib/libc/gb/sfr.s b/gbdk-lib/libc/gb/sfr.s @@ -1,167 +1,173 @@ .area _SFR (ABS) .org 0xFF00 -_P1_REG:: ; Joystick: 1.1.P15.P14.P13.P12.P11.P10 */ +_P1_REG:: ; Joystick: 1.1.P15.P14.P13.P12.P11.P10 .ds 1 .org 0xFF01 -_SB_REG:: ; Serial IO data buffer */ +_SB_REG:: ; Serial IO data buffer .ds 1 .org 0xFF02 -_SC_REG:: ; Serial IO control register */ +_SC_REG:: ; Serial IO control register .ds 1 .org 0xFF04 -_DIV_REG:: ; Divider register */ +_DIV_REG:: ; Divider register .ds 1 .org 0xFF05 -_TIMA_REG:: ; Timer counter */ +_TIMA_REG:: ; Timer counter .ds 1 .org 0xFF06 -_TMA_REG:: ; Timer modulo */ +_TMA_REG:: ; Timer modulo .ds 1 .org 0xFF07 -_TAC_REG:: ; Timer control */ +_TAC_REG:: ; Timer control .ds 1 .org 0xFF0F -_IF_REG:: ; Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL */ +_IF_REG:: ; Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL .ds 1 .org 0xFF10 -_NR10_REG:: ; Sound register */ +_NR10_REG:: ; Sound register .ds 1 .org 0xFF11 -_NR11_REG:: ; Sound register */ +_NR11_REG:: ; Sound register .ds 1 .org 0xFF12 -_NR12_REG:: ; Sound register */ +_NR12_REG:: ; Sound register .ds 1 .org 0xFF13 -_NR13_REG:: ; Sound register */ +_NR13_REG:: ; Sound register .ds 1 .org 0xFF14 -_NR14_REG:: ; Sound register */ +_NR14_REG:: ; Sound register .ds 1 .org 0xFF16 -_NR21_REG:: ; Sound register */ +_NR21_REG:: ; Sound register .ds 1 .org 0xFF17 -_NR22_REG:: ; Sound register */ +_NR22_REG:: ; Sound register .ds 1 .org 0xFF18 -_NR23_REG:: ; Sound register */ +_NR23_REG:: ; Sound register .ds 1 .org 0xFF19 -_NR24_REG:: ; Sound register */ +_NR24_REG:: ; Sound register .ds 1 .org 0xFF1A -_NR30_REG:: ; Sound register */ +_NR30_REG:: ; Sound register .ds 1 .org 0xFF1B -_NR31_REG:: ; Sound register */ +_NR31_REG:: ; Sound register .ds 1 .org 0xFF1C -_NR32_REG:: ; Sound register */ +_NR32_REG:: ; Sound register .ds 1 .org 0xFF1D -_NR33_REG:: ; Sound register */ +_NR33_REG:: ; Sound register .ds 1 .org 0xFF1E -_NR34_REG:: ; Sound register */ +_NR34_REG:: ; Sound register .ds 1 .org 0xFF20 -_NR41_REG:: ; Sound register */ +_NR41_REG:: ; Sound register .ds 1 .org 0xFF21 -_NR42_REG:: ; Sound register */ +_NR42_REG:: ; Sound register .ds 1 .org 0xFF22 -_NR43_REG:: ; Sound register */ +_NR43_REG:: ; Sound register .ds 1 .org 0xFF23 -_NR44_REG:: ; Sound register */ +_NR44_REG:: ; Sound register .ds 1 .org 0xFF24 -_NR50_REG:: ; Sound register */ +_NR50_REG:: ; Sound register .ds 1 .org 0xFF25 -_NR51_REG:: ; Sound register */ +_NR51_REG:: ; Sound register .ds 1 .org 0xFF26 -_NR52_REG:: ; Sound register */ +_NR52_REG:: ; Sound register .ds 1 .org 0xFF40 -_LCDC_REG:: ; LCD control */ +_LCDC_REG:: ; LCD control .ds 1 .org 0xFF41 -_STAT_REG:: ; LCD status */ +_STAT_REG:: ; LCD status .ds 1 .org 0xFF42 -_SCY_REG:: ; Scroll Y */ +_SCY_REG:: ; Scroll Y .ds 1 .org 0xFF43 -_SCX_REG:: ; Scroll X */ +_SCX_REG:: ; Scroll X .ds 1 .org 0xFF44 -_LY_REG:: ; LCDC Y-coordinate */ +_LY_REG:: ; LCDC Y-coordinate .ds 1 .org 0xFF45 -_LYC_REG:: ; LY compare */ +_LYC_REG:: ; LY compare .ds 1 .org 0xFF46 -_DMA_REG:: ; DMA transfer */ +_DMA_REG:: ; DMA transfer .ds 1 .org 0xFF47 -_BGP_REG:: ; BG palette data */ +_BGP_REG:: ; BG palette data .ds 1 .org 0xFF48 -_OBP0_REG:: ; OBJ palette 0 data */ +_OBP0_REG:: ; OBJ palette 0 data .ds 1 .org 0xFF49 -_OBP1_REG:: ; OBJ palette 1 data */ +_OBP1_REG:: ; OBJ palette 1 data .ds 1 .org 0xFF4A -_WY_REG:: ; Window Y coordinate */ +_WY_REG:: ; Window Y coordinate .ds 1 .org 0xFF4B -_WX_REG:: ; Window X coordinate */ +_WX_REG:: ; Window X coordinate .ds 1 .org 0xFF4D -_KEY1_REG:: ; CPU speed */ +_KEY1_REG:: ; CPU speed .ds 1 .org 0xFF4F -_VBK_REG:: ; VRAM bank */ +_VBK_REG:: ; VRAM bank .ds 1 .org 0xFF51 -_HDMA1_REG:: ; DMA control 1 */ +_HDMA1_REG:: ; DMA control 1 .ds 1 .org 0xFF52 -_HDMA2_REG:: ; DMA control 2 */ +_HDMA2_REG:: ; DMA control 2 .ds 1 .org 0xFF53 -_HDMA3_REG:: ; DMA control 3 */ +_HDMA3_REG:: ; DMA control 3 .ds 1 .org 0xFF54 -_HDMA4_REG:: ; DMA control 4 */ +_HDMA4_REG:: ; DMA control 4 .ds 1 .org 0xFF55 -_HDMA5_REG:: ; DMA control 5 */ +_HDMA5_REG:: ; DMA control 5 .ds 1 .org 0xFF56 -_RP_REG:: ; IR port */ +_RP_REG:: ; IR port .ds 1 .org 0xFF68 -_BCPS_REG:: ; BG color palette specification */ +_BCPS_REG:: ; BG color palette specification .ds 1 .org 0xFF69 -_BCPD_REG:: ; BG color palette data */ +_BCPD_REG:: ; BG color palette data .ds 1 .org 0xFF6A -_OCPS_REG:: ; OBJ color palette specification */ +_OCPS_REG:: ; OBJ color palette specification .ds 1 .org 0xFF6B _OCPD_REG:: ; OBJ color palette data .ds 1 .org 0xFF70 -_SVBK_REG:: ; WRAM bank */ +_SVBK_REG:: ; WRAM bank + .ds 1 + .org 0xFF76 +_PCM12_REG:: ; Sound channel 1&2 PCM amplitude (R) + .ds 1 + .org 0xFF77 +_PCM34_REG:: ; Sound channel 3&4 PCM amplitude (R) .ds 1 .org 0xFFFF -_IE_REG:: ; Interrupt enable */ +_IE_REG:: ; Interrupt enable .ds 1
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