gbdk-2020 | GameBoy Development Kit |
| download: https://git.y1.nz/archives/gbdk.tar.gz | |
| README | Files | Log | Refs | LICENSE |
commit 97f7794d03c1c1f2ac773ab8f2cc807996787491 parent ecc76ddc9d888aac1e72195106b253fd8b0b5d80 Author: Toxa <untoxa@mail.ru> Date: Tue, 13 Jul 2021 23:06:34 +0300 some more definitions Diffstat:
| M | gbdk-lib/include/gb/gb.h | 3 | +++ |
| M | gbdk-lib/include/gb/hardware.h | 31 | +++++++++++++++++++++++++++++-- |
| M | gbdk-lib/libc/gb/sfr.s | 139 | ++++++++++++++++++++++++++++++++++++++++++++++--------------------------------- |
3 files changed, 113 insertions(+), 60 deletions(-)
diff --git a/gbdk-lib/include/gb/gb.h b/gbdk-lib/include/gb/gb.h @@ -70,6 +70,9 @@ #define S_PRIORITY 0x80U /* Interrupt flags */ +/** Disable calling of interrupt service routines + */ +#define EMPTY_IFLAG 0x00U /** VBlank Interrupt occurs at the start of the vertical blank. During this period the video ram may be freely accessed. diff --git a/gbdk-lib/include/gb/hardware.h b/gbdk-lib/include/gb/hardware.h @@ -1,6 +1,6 @@ /** @file gb/hardware.h Defines that let the GB's hardware registers be accessed - from C. + from C. See the @ref Pandocs for more details on each register. */ @@ -9,8 +9,35 @@ #include <types.h> +#define __BYTES extern UBYTE +#define __BYTE_REG extern volatile UBYTE #define __REG extern volatile __sfr +/** Memoty map */ + +__BYTES _VRAM[]; +__BYTES _VRAM8000[]; +__BYTES _VRAM8800[]; +__BYTES _VRAM9000[]; +__BYTES _SCRN0[]; +__BYTES _SCRN1[]; +__BYTES _SRAM[]; +__BYTES _RAM[]; +__BYTES _RAMBANK[]; +__BYTES _OAMRAM[]; +__BYTE_REG _IO[]; +__BYTE_REG _AUD3WAVERAM[]; +__BYTE_REG _HRAM[]; + +/** MBC5 registers */ + +__BYTE_REG rRAMG; +__BYTE_REG rROMB0; +__BYTE_REG rROMB1; +__BYTE_REG rRAMB; + +/** IO Registers */ + __REG P1_REG; /** Joystick: 1.1.P15.P14.P13.P12.P11.P10 */ #define rP1 P1_REG @@ -120,7 +147,7 @@ __REG NR52_REG; /** Sound Master on/off */ #define AUDENA_ON 0b10000000u #define AUDENA_OFF 0b00000000u -extern UBYTE PCM_SAMPLE[16]; /** PCM sample */ +__BYTE_REG AUD3WAVE[16]; __REG LCDC_REG; /** LCD control */ #define rLCDC LCDC_REG diff --git a/gbdk-lib/libc/gb/sfr.s b/gbdk-lib/libc/gb/sfr.s @@ -1,61 +1,84 @@ -_P1_REG = 0xFF00 ; Joystick: 1.1.P15.P14.P13.P12.P11.P10 -_SB_REG = 0xFF01 ; Serial IO data buffer -_SC_REG = 0xFF02 ; Serial IO control register -_DIV_REG = 0xFF04 ; Divider register -_TIMA_REG = 0xFF05 ; Timer counter -_TMA_REG = 0xFF06 ; Timer modulo -_TAC_REG = 0xFF07 ; Timer control -_IF_REG = 0xFF0F ; Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL -_NR10_REG = 0xFF10 ; Sound register -_NR11_REG = 0xFF11 ; Sound register -_NR12_REG = 0xFF12 ; Sound register -_NR13_REG = 0xFF13 ; Sound register -_NR14_REG = 0xFF14 ; Sound register -_NR21_REG = 0xFF16 ; Sound register -_NR22_REG = 0xFF17 ; Sound register -_NR23_REG = 0xFF18 ; Sound register -_NR24_REG = 0xFF19 ; Sound register -_NR30_REG = 0xFF1A ; Sound register -_NR31_REG = 0xFF1B ; Sound register -_NR32_REG = 0xFF1C ; Sound register -_NR33_REG = 0xFF1D ; Sound register -_NR34_REG = 0xFF1E ; Sound register -_NR41_REG = 0xFF20 ; Sound register -_NR42_REG = 0xFF21 ; Sound register -_NR43_REG = 0xFF22 ; Sound register -_NR44_REG = 0xFF23 ; Sound register -_NR50_REG = 0xFF24 ; Sound register -_NR51_REG = 0xFF25 ; Sound register -_NR52_REG = 0xFF26 ; Sound register -_PCM_SAMPLE = 0xFF30 ; PCM wave pattern -_LCDC_REG = 0xFF40 ; LCD control -_STAT_REG = 0xFF41 ; LCD status -_SCY_REG = 0xFF42 ; Scroll Y -_SCX_REG = 0xFF43 ; Scroll X -_LY_REG = 0xFF44 ; LCDC Y-coordinate -_LYC_REG = 0xFF45 ; LY compare -_DMA_REG = 0xFF46 ; DMA transfer -_BGP_REG = 0xFF47 ; BG palette data -_OBP0_REG = 0xFF48 ; OBJ palette 0 data -_OBP1_REG = 0xFF49 ; OBJ palette 1 data -_WY_REG = 0xFF4A ; Window Y coordinate -_WX_REG = 0xFF4B ; Window X coordinate -_KEY1_REG = 0xFF4D ; CPU speed -_VBK_REG = 0xFF4F ; VRAM bank -_HDMA1_REG = 0xFF51 ; DMA control 1 -_HDMA2_REG = 0xFF52 ; DMA control 2 -_HDMA3_REG = 0xFF53 ; DMA control 3 -_HDMA4_REG = 0xFF54 ; DMA control 4 -_HDMA5_REG = 0xFF55 ; DMA control 5 -_RP_REG = 0xFF56 ; IR port -_BCPS_REG = 0xFF68 ; BG color palette specification -_BCPD_REG = 0xFF69 ; BG color palette data -_OCPS_REG = 0xFF6A ; OBJ color palette specification -_OCPD_REG = 0xFF6B ; OBJ color palette data -_SVBK_REG = 0xFF70 ; WRAM bank -_PCM12_REG = 0xFF76 ; Sound channel 1&2 PCM amplitude (R) -_PCM34_REG = 0xFF77 ; Sound channel 3&4 PCM amplitude (R) -_IE_REG = 0xFFFF ; Interrupt enable +__VRAM = 0x8000 +__VRAM8000 = 0x8000 +__VRAM8800 = 0x8800 +__VRAM9000 = 0x9000 +__SCRN0 = 0x9800 +__SCRN1 = 0x9C00 +__SRAM = 0xA000 +__RAM = 0xC000 +__RAMBANK = 0xD000 +__OAMRAM = 0xFE00 +__IO = 0xFF00 +__AUD3WAVERAM = 0xFF30 +__HRAM = 0xFF80 + +.globl __VRAM, __VRAM8000, __VRAM8800, __VRAM9000, __SCRN0, __SCRN1, __SRAM, __RAM, __RAMBANK, __OAMRAM, __IO, __AUD3WAVERAM, __HRAM + +_rRAMG = 0x0000 +_rROMB0 = 0x2000 +_rROMB1 = 0x3000 +_rRAMB = 0x4000 + +.globl _rRAMG, _rROMB0, _rROMB1, _rRAMB + +_P1_REG = 0xFF00 ; Joystick: 1.1.P15.P14.P13.P12.P11.P10 +_SB_REG = 0xFF01 ; Serial IO data buffer +_SC_REG = 0xFF02 ; Serial IO control register +_DIV_REG = 0xFF04 ; Divider register +_TIMA_REG = 0xFF05 ; Timer counter +_TMA_REG = 0xFF06 ; Timer modulo +_TAC_REG = 0xFF07 ; Timer control +_IF_REG = 0xFF0F ; Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL +_NR10_REG = 0xFF10 ; Sound register +_NR11_REG = 0xFF11 ; Sound register +_NR12_REG = 0xFF12 ; Sound register +_NR13_REG = 0xFF13 ; Sound register +_NR14_REG = 0xFF14 ; Sound register +_NR21_REG = 0xFF16 ; Sound register +_NR22_REG = 0xFF17 ; Sound register +_NR23_REG = 0xFF18 ; Sound register +_NR24_REG = 0xFF19 ; Sound register +_NR30_REG = 0xFF1A ; Sound register +_NR31_REG = 0xFF1B ; Sound register +_NR32_REG = 0xFF1C ; Sound register +_NR33_REG = 0xFF1D ; Sound register +_NR34_REG = 0xFF1E ; Sound register +_NR41_REG = 0xFF20 ; Sound register +_NR42_REG = 0xFF21 ; Sound register +_NR43_REG = 0xFF22 ; Sound register +_NR44_REG = 0xFF23 ; Sound register +_NR50_REG = 0xFF24 ; Sound register +_NR51_REG = 0xFF25 ; Sound register +_NR52_REG = 0xFF26 ; Sound register +_PCM_SAMPLE = 0xFF30 ; PCM wave pattern +_LCDC_REG = 0xFF40 ; LCD control +_STAT_REG = 0xFF41 ; LCD status +_SCY_REG = 0xFF42 ; Scroll Y +_SCX_REG = 0xFF43 ; Scroll X +_LY_REG = 0xFF44 ; LCDC Y-coordinate +_LYC_REG = 0xFF45 ; LY compare +_DMA_REG = 0xFF46 ; DMA transfer +_BGP_REG = 0xFF47 ; BG palette data +_OBP0_REG = 0xFF48 ; OBJ palette 0 data +_OBP1_REG = 0xFF49 ; OBJ palette 1 data +_WY_REG = 0xFF4A ; Window Y coordinate +_WX_REG = 0xFF4B ; Window X coordinate +_KEY1_REG = 0xFF4D ; CPU speed +_VBK_REG = 0xFF4F ; VRAM bank +_HDMA1_REG = 0xFF51 ; DMA control 1 +_HDMA2_REG = 0xFF52 ; DMA control 2 +_HDMA3_REG = 0xFF53 ; DMA control 3 +_HDMA4_REG = 0xFF54 ; DMA control 4 +_HDMA5_REG = 0xFF55 ; DMA control 5 +_RP_REG = 0xFF56 ; IR port +_BCPS_REG = 0xFF68 ; BG color palette specification +_BCPD_REG = 0xFF69 ; BG color palette data +_OCPS_REG = 0xFF6A ; OBJ color palette specification +_OCPD_REG = 0xFF6B ; OBJ color palette data +_SVBK_REG = 0xFF70 ; WRAM bank +_PCM12_REG = 0xFF76 ; Sound channel 1&2 PCM amplitude (R) +_PCM34_REG = 0xFF77 ; Sound channel 3&4 PCM amplitude (R) +_IE_REG = 0xFFFF ; Interrupt enable .globl _P1_REG .globl _SB_REG, _SC_REG
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