gbdk-2020 | GameBoy Development Kit |
| download: https://git.y1.nz/archives/gbdk.tar.gz | |
| README | Files | Log | Refs | LICENSE |
commit c2929d709cb8eeca3820e2029fe5663f98cfe15d parent 7f26a1ab846c80ffbb968e0045ffd89a49817be6 Author: Toxa <untoxa@mail.ru> Date: Thu, 1 Sep 2022 12:36:07 +0300 Merge branch 'develop' of https://github.com/gbdk-2020/gbdk-2020 into develop Diffstat:
| A | LICENSE | 35 | +++++++++++++++++++++++++++++++++++ |
| M | Makefile | 2 | +- |
| M | gbdk-lib/libc/targets/mos6502/nes/crt0.s | 203 | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------------- |
| R | license/LICENSE_GPLV2_LE -> licenses/LICENSE_GPLV2_LE | 0 | |
| R | license/LICENSE_SDCC -> licenses/LICENSE_SDCC | 0 | |
| R | license/LICENSE_bankpack -> licenses/LICENSE_bankpack | 0 | |
| R | license/LICENSE_crashhandler -> licenses/LICENSE_crashhandler | 0 | |
| R | license/LICENSE_gbcompress -> licenses/LICENSE_gbcompress | 0 | |
| R | license/LICENSE_ihxcheck -> licenses/LICENSE_ihxcheck | 0 | |
| R | license/LICENSE_lcc -> licenses/LICENSE_lcc | 0 | |
| R | license/LICENSE_makebin -> licenses/LICENSE_makebin | 0 | |
| R | license/LICENSE_makecom -> licenses/LICENSE_makecom | 0 | |
| R | license/LICENSE_png2asset -> licenses/LICENSE_png2asset | 0 |
13 files changed, 186 insertions(+), 54 deletions(-)
diff --git a/LICENSE b/LICENSE @@ -0,0 +1,35 @@ + + +### Overview of Licenses in GBDK-2020 + +See the relevant licensing files in the LICENSES folder for details on the entries below + + +### GBDK Library & Makefiles: +GPLv2+LE (linking exception). Some files from SDCC, some from the historical GBDK that were originally LGPL and have been relicensed to GPLv2+LE (linking exception) to match the SDCC ones in 2022 by permission of original authors. +- LICENSE_SDCC +- LICENSE_GPLV2_LE + + +### Crash handler in the GBDK Library +MIT License: https://github.com/ISSOtm/gb-starter-kit/ +- LICENSE_crashhandler + + +### makebin: +zlib/libpng License +According to: http://sdcc.sourceforge.net/ + + +### bankpack, ihxcheck, gbcompress, makecom: +Public Domain. @bbbbbr is the original author + + +### png2asset: +MIT License. @Zal0 is the original author + additional contributors + + +### LCC front end / compiler driver: +LCC License, traditionally named as the "CPYRIGHT" file + + diff --git a/Makefile b/Makefile @@ -36,7 +36,7 @@ GBDKSUPPORTDIR = $(TOPDIR)/gbdk-support # Directory with docs config and output (via doxygen) GBDKDOCSDIR = $(TOPDIR)/docs -GBDKLICENSEDIR = $(TOPDIR)/license +GBDKLICENSEDIR = $(TOPDIR)/licenses # Doxygen command and version check info DOXYGENCMD = doxygen diff --git a/gbdk-lib/libc/targets/mos6502/nes/crt0.s b/gbdk-lib/libc/targets/mos6502/nes/crt0.s @@ -14,6 +14,22 @@ _shadow_OAM = 0x200 _attribute_shadow = 0x188 ; Transfer buffer (lower half of hardware stack) _vram_transfer_buffer = 0x100 +; +; Format of transfer buffer +; +; 0: Data length +; 1: 4 if inc-by-32, 0 if inc-by-1 +; 2: PPUADDR_HI +; 3: PPUADDR_LO +; 4: ...N data bytes... +; +VRAM_HDR_SIZEOF = 4 +VRAM_HDR_LENGTH = 0 +VRAM_HDR_DIRECTION = 1 +VRAM_HDR_PPUHI = 2 +VRAM_HDR_PPULO = 3 +; Number of 8-cycles available each frame for transfer buffer +VRAM_DELAY_CYCLES_X8 = 170 ; Declare a dummy symbol for banking ; TODO: Make banking actually work @@ -39,6 +55,16 @@ b_wait_frames = 0 .endm .endm +.macro VRAM_BUFFER_LOCK + clc + ror *__crt0_drawListValid +.endm + +.macro VRAM_BUFFER_UNLOCK + sec + ror *__crt0_drawListValid +.endm + .area ZP (PAG) __shadow_OAM_base:: .ds 1 __current_bank:: .ds 1 @@ -52,7 +78,6 @@ __crt0_NMI_insideNMI: .ds 1 __crt0_ScrollHV: .ds 1 __crt0_drawListValid: .ds 1 __crt0_drawListNumDelayCycles_x8: .ds 1 -__crt0_drawListPosR: .ds 1 __crt0_drawListPosW: .ds 1 __crt0_textPPUAddr: .ds 2 __crt0_NMITEMP: .ds 4 @@ -62,6 +87,8 @@ __crt0_textTemp: .ds 1 _bkg_scroll_x:: .ds 1 _bkg_scroll_y:: .ds 1 _attribute_row_dirty:: .ds 1 +.crt0_textStringBegin: .ds 1 +.crt0_forced_blanking: .ds 1 ;; **************************************** @@ -201,7 +228,17 @@ __crt0_doSpriteDMA_loop: DoUpdateVRAM: WRITE_PALETTE_SHADOW bit *__crt0_drawListValid - bpl DoUpdateVRAM_drawListInvalid + bmi DoUpdateVRAM_drawListValid +DoUpdateVRAM_drawListInvalid: + ; Delay exactly 1633 cycles to keep timing consistent + ldx #(VRAM_DELAY_CYCLES_X8+7) +DoUpdateVRAM_invalid_loop: + lda *__crt0_drawListNumDelayCycles_x8 + dex + bne DoUpdateVRAM_invalid_loop + nop + rts +DoUpdateVRAM_drawListValid: jsr ProcessDrawList ; Delay up to 167*8-1 = 1575 cycles (value set by draw list creation code) ; ...plus fixed-cost of 56 cycles @@ -210,31 +247,11 @@ DoUpdateVRAM_valid_loop: stx *__crt0_drawListNumDelayCycles_x8 dex bne DoUpdateVRAM_valid_loop - lda #169 - sta *__crt0_drawListNumDelayCycles_x8 - rts -DoUpdateVRAM_drawListInvalid: - ; Delay exactly 1633 cyles to keep timing consistent - ldx #176 -DoUpdateVRAM_invalid_loop: - stx *__crt0_drawListNumDelayCycles_x8 - dex - bne DoUpdateVRAM_invalid_loop - nop - nop - lda #169 + lda #VRAM_DELAY_CYCLES_X8 sta *__crt0_drawListNumDelayCycles_x8 rts ; -; Format of draw list -; -; 0: Data length -; 1: 4 if inc-by-32, 0 if inc-by-1 -; 2: PPUADDR_HI -; 3: PPUADDR_LO -; 4: ...N data bytes... -; ; Number of cycles spent = 19 + 21 + 48*NumTransfers + 8*NumBytesTransferred ; = 56 + 48*NumTransfers + 8*NumBytesTransferred ; = 8 * (7 + 6*NumTransfers + NumBytesTransferred) @@ -247,11 +264,10 @@ ProcessDrawList: sta *ProcessDrawList_addr+1 ; +3 tsx ; +2 stx *ProcessDrawList_tempX ; +3 - ldx #0 ;drawListPosR ; +2 - dex ; +2 + ldx #0xFF ; +2 txs ; +2 jmp ProcessDrawList_DoOneTransfer ; +3 - ; Total = 2 + 3 + 2 + 3 + 2 + 2 + 2 + 3 = 19 fixed-cost entry + ; Total = 2 + 3 + 2 + 3 + 2 + 2 + 3 = 17 fixed-cost entry .bndry 0x100 ProcessDrawList_UnrolledCopyLoop: @@ -279,16 +295,13 @@ ProcessDrawList_DoOneTransfer: ; 4 + 3 + 14 = 7 + 14 = 21 fixed-cost exit ProcessDrawList_EndOfList: - tsx ; +2 - inx ; +2 - stx *__crt0_drawListPosR ; +3 ldx *ProcessDrawList_tempX ; +3 txs ; +2 lda #0 ; +2 sta *__crt0_drawListPosW ; +3 sta *__crt0_drawListValid ; +3 rts ; +6 - ; = 2 + 2 + 3 + 3 + 2 + 2 + 3 + 3 + 6 = 26 + ; = 3 + 2 + 2 + 3 + 3 + 6 = 19 .bndry 0x100 ProcessDrawList_NumBytesToAddress: @@ -316,18 +329,87 @@ _writeNametableByte:: rol *__crt0_textPPUAddr+1 ora .identity,x sta *__crt0_textPPUAddr -; Prevent main code from writing too much data by waiting for NMI to flush transfer buffer if >= 32 bytes + ; If we're currently in forced blanking mode, use direct writes instead of transfer buffer + bit *.crt0_forced_blanking + bpl 1$ + lda *__crt0_textPPUAddr+1 + sta PPUADDR + lda *__crt0_textPPUAddr + sta PPUADDR + lda #0 + rol + asl + asl + ora *_shadow_PPUCTRL + sta PPUCTRL + pla + sta PPUDATA + ; Increment PPU addr + lda *__crt0_textPPUAddr + clc + adc #1 + sta *__crt0_textPPUAddr + lda *(__crt0_textPPUAddr+1) + adc #0 + sta *(__crt0_textPPUAddr+1) + rts +1$: _writeNametableByteWaitForFlush: ldy *__crt0_drawListPosW tya ; Limit when (slightly more than) equal to 80 bytes, to avoid overrunning vblank time cmp #80 bcs _writeNametableByteWaitForFlush - ; Just write each character as a separate single-byte write - ; TODO: Optimize to handle continuous characters as multi-byte transfer for less blocking. + VRAM_BUFFER_LOCK + ; First check if we can append to previously added stripe + ldy *.crt0_textStringBegin + ; Only append if current vram buffer pointer directly follows previous stripe + tya clc - ror *__crt0_drawListValid + adc _vram_transfer_buffer+VRAM_HDR_LENGTH,y + adc #VRAM_HDR_SIZEOF + cmp *__crt0_drawListPosW + bne 2$ + ; Only append if previous stripe was horizontal + lda _vram_transfer_buffer+VRAM_HDR_DIRECTION,y + bne 2$ + ; Only append if PPU address following previous stripe matches desired PPU address + lda _vram_transfer_buffer+VRAM_HDR_PPULO,y + clc + adc _vram_transfer_buffer+VRAM_HDR_LENGTH,y + sta *.tmp + lda _vram_transfer_buffer+VRAM_HDR_PPUHI,y + adc #0 + ; Check against textPPUAddr + cmp *__crt0_textPPUAddr+1 + bne 2$ + lda *.tmp + cmp *__crt0_textPPUAddr + bne 2$ + jmp _writeNametableByte_continue +2$: + jmp _writeNametableByte_new + +_writeNametableByte_end: + ; Increment PPU addr + lda *__crt0_textPPUAddr + clc + adc #1 + sta *__crt0_textPPUAddr + lda *(__crt0_textPPUAddr+1) + adc #0 + sta *(__crt0_textPPUAddr+1) + sty *__crt0_drawListPosW + VRAM_BUFFER_UNLOCK + ldy *__crt0_textTemp + rts + +; +; Writes a new nametable byte, effectively beginning a new stripe +; +_writeNametableByte_new: ldy *__crt0_drawListPosW + sty *.crt0_textStringBegin ; Number of bytes lda #1 sta _vram_transfer_buffer,y @@ -355,26 +437,34 @@ _writeNametableByteWaitForFlush: ; Each new write operation adds 48 cycles + 8 cycles per written byte, i.e.: ; NumDelayCycles_x8 -= 6 * numberOfWriteCommands + numWrittenBytes ; - dec *__crt0_drawListNumDelayCycles_x8 - dec *__crt0_drawListNumDelayCycles_x8 - dec *__crt0_drawListNumDelayCycles_x8 - dec *__crt0_drawListNumDelayCycles_x8 - dec *__crt0_drawListNumDelayCycles_x8 - dec *__crt0_drawListNumDelayCycles_x8 - dec *__crt0_drawListNumDelayCycles_x8 - ; Increment PPU addr - lda *__crt0_textPPUAddr + ; __crt0_drawListNumDelayCycles_x8 -= 7 + lda *__crt0_drawListNumDelayCycles_x8 + sec + sbc #7 + sta *__crt0_drawListNumDelayCycles_x8 + jmp _writeNametableByte_end + +; +; Continues the previously started stripe by adding an additional byte to it +; +_writeNametableByte_continue: + ; Increase number of bytes in header + ldy *.crt0_textStringBegin + lda _vram_transfer_buffer,y clc adc #1 - sta *__crt0_textPPUAddr - lda *(__crt0_textPPUAddr+1) - adc #0 - sta *(__crt0_textPPUAddr+1) - sty *__crt0_drawListPosW - sec - ror *__crt0_drawListValid - ldy *__crt0_textTemp - rts + sta _vram_transfer_buffer,y + ; Write new byte + ldy *__crt0_drawListPosW + pla + sta _vram_transfer_buffer,y + iny + ; zero byte at end + lda #0 + sta _vram_transfer_buffer,y + ; Decrease x8 cycle delay by 1 + dec *__crt0_drawListNumDelayCycles_x8 + jmp _writeNametableByte_end __crt0_IRQ: jmp __crt0_IRQ @@ -499,9 +589,10 @@ __crt0_RESET_bankSwitchValue: sta *__crt0_textPPUAddr lda #>0x2041 sta *(__crt0_textPPUAddr+1) + lda #VRAM_DELAY_CYCLES_X8 + sta *__crt0_drawListNumDelayCycles_x8 lda #0 sta *__crt0_drawListPosW - sta *__crt0_drawListPosR ; lda #(PPUMASK_SHOW_BG | PPUMASK_SHOW_SPR | PPUMASK_SHOW_BG_LC | PPUMASK_SHOW_SPR_LC) sta *_shadow_PPUMASK @@ -523,6 +614,9 @@ _display_off:: and #~(PPUMASK_SHOW_BG | PPUMASK_SHOW_SPR) sta *_shadow_PPUMASK sta PPUMASK + ; Set forced blanking bit + sec + ror *.crt0_forced_blanking rts .display_on:: @@ -531,6 +625,9 @@ _display_on:: ora #(PPUMASK_SHOW_BG | PPUMASK_SHOW_SPR) sta *_shadow_PPUMASK sta PPUMASK + ; Clear forced blanking bit + clc + ror *.crt0_forced_blanking rts ; Interrupt / RESET vector table diff --git a/license/LICENSE_GPLV2_LE b/licenses/LICENSE_GPLV2_LE diff --git a/license/LICENSE_SDCC b/licenses/LICENSE_SDCC diff --git a/license/LICENSE_bankpack b/licenses/LICENSE_bankpack diff --git a/license/LICENSE_crashhandler b/licenses/LICENSE_crashhandler diff --git a/license/LICENSE_gbcompress b/licenses/LICENSE_gbcompress diff --git a/license/LICENSE_ihxcheck b/licenses/LICENSE_ihxcheck diff --git a/license/LICENSE_lcc b/licenses/LICENSE_lcc diff --git a/license/LICENSE_makebin b/licenses/LICENSE_makebin diff --git a/license/LICENSE_makecom b/licenses/LICENSE_makecom diff --git a/license/LICENSE_png2asset b/licenses/LICENSE_png2asset
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