git.y1.nz

commit f331ec9e1d0a364924a12be89cce03107e8a20a2
parent 5a2d610fe739d7111dfdcda0803fc5363e5cb642
Author: Toxa <untoxa@mail.ru>
Date:   Fri, 28 Jul 2023 13:02:46 +0300

GB: rewrite set_vram_byte(), new WAIT_STAT_HL macro

Diffstat:
M
gbdk-lib/include/gb/gb.h
2
+-
M
gbdk-lib/libc/targets/sm83/ap/global.s
6
++++++
M
gbdk-lib/libc/targets/sm83/duck/global.s
6
++++++
M
gbdk-lib/libc/targets/sm83/gb/global.s
6
++++++
M
gbdk-lib/libc/targets/sm83/set_tile.s
10
+---------

5 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/gbdk-lib/include/gb/gb.h b/gbdk-lib/include/gb/gb.h
@@ -882,7 +882,7 @@ void hiramcpy(uint8_t dst, const void *src, uint8_t n) OLDCALL PRESERVES_REGS(b,
  * @param addr address to write to
  * @param v value
  */
-void set_vram_byte(uint8_t * addr, uint8_t v) OLDCALL PRESERVES_REGS(b, c);
+void set_vram_byte(uint8_t * addr, uint8_t v) PRESERVES_REGS(b, c);
 
 /**
  * Get byte from vram at given memory location
diff --git a/gbdk-lib/libc/targets/sm83/ap/global.s b/gbdk-lib/libc/targets/sm83/ap/global.s
@@ -479,6 +479,12 @@ lbl:    LDH     A, (.STAT)
         JR      NZ, lbl
 .endm
 
+.macro WAIT_STAT_HL ?lbl
+        LD      HL, #rSTAT
+lbl:    BIT     #STATF_B_BUSY, (HL)
+        JR      NZ, lbl
+.endm
+
 .macro ADD_A_REG16 regH regL
         ADD     regL
         LD      regL, A
diff --git a/gbdk-lib/libc/targets/sm83/duck/global.s b/gbdk-lib/libc/targets/sm83/duck/global.s
@@ -479,6 +479,12 @@ lbl:    LDH     A, (.STAT)
         JR      NZ, lbl
 .endm
 
+.macro WAIT_STAT_HL ?lbl
+        LD      HL, #rSTAT
+lbl:    BIT     #STATF_B_BUSY, (HL)
+        JR      NZ, lbl
+.endm
+
 .macro ADD_A_REG16 regH regL
         ADD     regL
         LD      regL, A
diff --git a/gbdk-lib/libc/targets/sm83/gb/global.s b/gbdk-lib/libc/targets/sm83/gb/global.s
@@ -479,6 +479,12 @@ lbl:    LDH     A, (.STAT)
         JR      NZ, lbl
 .endm
 
+.macro WAIT_STAT_HL ?lbl
+        LD      HL, #rSTAT
+lbl:    BIT     #STATF_B_BUSY, (HL)
+        JR      NZ, lbl
+.endm
+
 .macro ADD_A_REG16 regH regL
         ADD     regL
         LD      regL, A
diff --git a/gbdk-lib/libc/targets/sm83/set_tile.s b/gbdk-lib/libc/targets/sm83/set_tile.s
@@ -3,17 +3,9 @@
 .area _CODE
 
 _set_vram_byte::
-        ; de = addr, hl = &t
-        ldhl    sp,#2
-        ld      a,(hl+)
-        ld      e, a
-        ld      a,(hl+)
-        ld      d, a
-
-        WAIT_STAT
+        WAIT_STAT_HL
 
         ; Write tile
-        ld      a,(hl)
         ld      (de),a
         ret
 

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