git.y1.nz

commit f567c7970893b4ee6819624e1cc3c8f9488d12ca
parent de93a83d4d189608c74b1d6dfe66ff40b4d3aab0
Author: Michel Iwaniec <46843052+michel-iwaniec@users.noreply.github.com>
Date:   Tue,  6 Feb 2024 15:48:50 +0000

Merge pull request #625 from michel-iwaniec/nes_transfer_buffer_optimization-cp

NES: Slight optimization of transfer buffer stripe setup cost
Diffstat:
M
gbdk-lib/libc/targets/mos6502/nes/crt0.s
10
+++-------
M
gbdk-lib/libc/targets/mos6502/nes/vram_transfer_buffer.s
27
+++++++++++++++++++--------

2 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/gbdk-lib/libc/targets/mos6502/nes/crt0.s b/gbdk-lib/libc/targets/mos6502/nes/crt0.s
@@ -96,6 +96,7 @@ i = i + 1
 .define ProcessDrawList_addr  "__crt0_NMITEMP+0"
 
 .bndry 0x100
+    nop         ; Pad to offset, to support zero-terminator value
 ProcessDrawList_UnrolledCopyLoop:
 .rept 32
 pla             ; +4
@@ -104,11 +105,6 @@ sta PPUDATA     ; +4
 ProcessDrawList_DoOneTransfer:
     pla                                         ; +4
     beq ProcessDrawList_EndOfList               ; +2/3
-    ; branchaddr = 128-4*num_bytes = NOT(4*num_bytes)+1+128 = NOT(4*num_bytes)+129
-    asl                                         ; +2
-    asl                                         ; +2
-    eor #0xFF                                   ; +2
-    adc #129                                    ; +2
     sta *ProcessDrawList_addr                   ; +3
     pla                                         ; +4
     sta PPUCTRL                                 ; +4
@@ -288,7 +284,7 @@ DoUpdateVRAM:
     bit *__vram_transfer_buffer_valid
     bmi DoUpdateVRAM_drawListValid
 DoUpdateVRAM_drawListInvalid:
-    ; Delay exactly 1633 cycles to keep timing consistent
+    ; Delay for remaining cycles to keep timing consistent
     ldx #(VRAM_DELAY_CYCLES_X8+7)
 DoUpdateVRAM_invalid_loop:
     lda *__vram_transfer_buffer_num_cycles_x8
@@ -298,7 +294,7 @@ DoUpdateVRAM_invalid_loop:
     rts
 DoUpdateVRAM_drawListValid:
     jsr ProcessDrawList
-    ; Delay up to 167*8-1 = 1575 cycles (value set by draw list creation code)
+    ; Delay for remaining cycles to keep timing consistent
     ; ...plus fixed-cost of 56 cycles
     ldx *__vram_transfer_buffer_num_cycles_x8
 DoUpdateVRAM_valid_loop:
diff --git a/gbdk-lib/libc/targets/mos6502/nes/vram_transfer_buffer.s b/gbdk-lib/libc/targets/mos6502/nes/vram_transfer_buffer.s
@@ -119,9 +119,9 @@ __vram_transfer_buffer_pos_old::        .ds 1
     clc
     adc #VRAM_HDR_SIZEOF
     sta *__vram_transfer_buffer_pos_w
-    ; __vram_transfer_buffer_num_cycles_x8 -= 6 (assumes carry clear)
+    ; __vram_transfer_buffer_num_cycles_x8 -= 5 (assumes carry clear)
     lda *__vram_transfer_buffer_num_cycles_x8
-    sbc #5
+    sbc #4
     sta *__vram_transfer_buffer_num_cycles_x8
     ldy *__vram_transfer_buffer_temp
     rts
@@ -146,10 +146,18 @@ __vram_transfer_buffer_pos_old::        .ds 1
     sec
     sbc *__vram_transfer_buffer_pos_old
     sbc #VRAM_HDR_SIZEOF
+    pha
+    ; branchaddr = 128-4*num_bytes + 1 = NOT(4*num_bytes)+1+128 + 1 = NOT(4*num_bytes)+130
+    asl
+    asl
+    eor #0xFF
+    adc #130
     ldy *__vram_transfer_buffer_pos_old
     sta __vram_transfer_buffer+VRAM_HDR_LENGTH,y
-    lda *__vram_transfer_buffer_num_cycles_x8
-    sbc __vram_transfer_buffer+VRAM_HDR_LENGTH,y
+    pla
+    eor #0xFF
+    sec
+    adc *__vram_transfer_buffer_num_cycles_x8
     sta *__vram_transfer_buffer_num_cycles_x8
     VRAM_BUFFER_UNLOCK
     ldy *__vram_transfer_buffer_temp
@@ -270,7 +278,7 @@ _set_vram_byte::
     sta __vram_transfer_buffer+VRAM_HDR_DIRECTION,y
     sta __vram_transfer_buffer+VRAM_HDR_SIZEOF+1,y
     ; Write length
-    lda #1
+    lda #(128-4*1 + 1)
     sta __vram_transfer_buffer+VRAM_HDR_LENGTH,y
     ; Write address
     lda *ppu_addr+1
@@ -286,9 +294,9 @@ _set_vram_byte::
     adc #VRAM_HDR_SIZEOF+1
     ; store new write pointer
     sta *__vram_transfer_buffer_pos_w
-    ; __vram_transfer_buffer_num_cycles_x8 -= 7 (assumes carry clear)
+    ; __vram_transfer_buffer_num_cycles_x8 -= 6 (assumes carry clear)
     lda *__vram_transfer_buffer_num_cycles_x8
-    sbc #6
+    sbc #5
     sta *__vram_transfer_buffer_num_cycles_x8
     VRAM_BUFFER_UNLOCK
     ; Return PPU address
@@ -319,7 +327,10 @@ _set_vram_byte::
 
 .ppu_stripe_append_1byte:
     ; Append 1 byte
-    inc __vram_transfer_buffer+VRAM_HDR_LENGTH,x
+    dec __vram_transfer_buffer+VRAM_HDR_LENGTH,x
+    dec __vram_transfer_buffer+VRAM_HDR_LENGTH,x
+    dec __vram_transfer_buffer+VRAM_HDR_LENGTH,x
+    dec __vram_transfer_buffer+VRAM_HDR_LENGTH,x
     lda *_set_vram_byte_PARM_2
     ldx *__vram_transfer_buffer_pos_w
     sta __vram_transfer_buffer,x

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