gbdk-2020 | GameBoy Development Kit |
| download: https://git.y1.nz/archives/gbdk.tar.gz | |
| README | Files | Log | Refs | LICENSE |
commit 375bc8cbb59bfb366260fe2a157275db84a5b320 parent 818d037217382fdd8d19d62e05242cec74ae0cf5 Author: Toxa <untoxa@mail.ru> Date: Tue, 13 Jul 2021 01:35:48 +0300 reorganize sfr.s Diffstat:
| M | gbdk-lib/include/gb/hardware.h | 118 | ++++++++++++++++++++++++++++++++++++++++--------------------------------------- |
| M | gbdk-lib/libc/gb/sfr.s | 260 | +++++++++++++++++++++++++++---------------------------------------------------- |
2 files changed, 147 insertions(+), 231 deletions(-)
diff --git a/gbdk-lib/include/gb/hardware.h b/gbdk-lib/include/gb/hardware.h @@ -11,7 +11,7 @@ #define __REG extern volatile __sfr -__REG P1_REG; /** Joystick: 1.1.P15.P14.P13.P12.P11.P10 */ +__REG P1_REG; /** Joystick: 1.1.P15.P14.P13.P12.P11.P10 */ #define rP1 P1_REG #define P1F_5 0b00100000u @@ -25,78 +25,78 @@ __REG P1_REG; /** Joystick: 1.1.P15.P14.P13.P12.P11.P10 */ #define P1F_GET_BTN P1F_4 #define P1F_GET_NONE (P1F_4 | P1F_5) -__REG SB_REG; /** Serial IO data buffer */ +__REG SB_REG; /** Serial IO data buffer */ #define rSB SB_REG -__REG SC_REG; /** Serial IO control register */ +__REG SC_REG; /** Serial IO control register */ #define rSC SC_REG -__REG DIV_REG; /** Divider register */ +__REG DIV_REG; /** Divider register */ #define rDIV DIV_REG -__REG TIMA_REG; /** Timer counter */ +__REG TIMA_REG; /** Timer counter */ #define rTIMA TIMA_REG -__REG TMA_REG; /** Timer modulo */ +__REG TMA_REG; /** Timer modulo */ #define rTMA TMA_REG -__REG TAC_REG; /** Timer control */ +__REG TAC_REG; /** Timer control */ #define rTAC TAC_REG -#define TACF_START 0b00000100u +#define TACF_START 0b00000100u #define TACF_STOP 0b00000000u #define TACF_4KHZ 0b00000000u #define TACF_16KHZ 0b00000011u #define TACF_65KHZ 0b00000010u #define TACF_262KHZ 0b00000001u -__REG IF_REG; /** Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL */ +__REG IF_REG; /** Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL */ #define rIF IF_REG -__REG NR10_REG; /** Sound Channel 1 Sweep */ +__REG NR10_REG; /** Sound Channel 1 Sweep */ #define rAUD1SWEEP NR10_REG #define AUD1SWEEP_UP 0b00000000u #define AUD1SWEEP_DOWN 0b00001000u -__REG NR11_REG; /** Sound Channel 1 Sound length/Wave pattern duty */ +__REG NR11_REG; /** Sound Channel 1 Sound length/Wave pattern duty */ #define rAUD1LEN NR11_REG -__REG NR12_REG; /** Sound Channel 1 Volume Envelope */ +__REG NR12_REG; /** Sound Channel 1 Volume Envelope */ #define rAUD1ENV NR12_REG -__REG NR13_REG; /** Sound Channel 1 Frequency Low */ +__REG NR13_REG; /** Sound Channel 1 Frequency Low */ #define rAUD1LOW NR13_REG -__REG NR14_REG; /** Sound Channel 1 Frequency High */ +__REG NR14_REG; /** Sound Channel 1 Frequency High */ #define rAUD1HIGH NR14_REG -__REG NR21_REG; /** Sound Channel 2 Tone */ +__REG NR21_REG; /** Sound Channel 2 Tone */ #define rAUD2LEN NR21_REG -__REG NR22_REG; /** Sound Channel 2 Volume Envelope */ +__REG NR22_REG; /** Sound Channel 2 Volume Envelope */ #define rAUD2ENV NR22_REG -__REG NR23_REG; /** Sound Channel 2 Frequency data Low */ +__REG NR23_REG; /** Sound Channel 2 Frequency data Low */ #define rAUD2LOW NR23_REG -__REG NR24_REG; /** Sound Channel 2 Frequency data High */ +__REG NR24_REG; /** Sound Channel 2 Frequency data High */ #define rAUD2HIGH NR24_REG -__REG NR30_REG; /** Sound Channel 3 Sound on/off */ +__REG NR30_REG; /** Sound Channel 3 Sound on/off */ #define rAUD3ENA NR30_REG -__REG NR31_REG; /** Sound Channel 3 Sound Length */ +__REG NR31_REG; /** Sound Channel 3 Sound Length */ #define rAUD3LEN NR31_REG -__REG NR32_REG; /** Sound Channel 3 Select output level */ +__REG NR32_REG; /** Sound Channel 3 Select output level */ #define rAUD3LEVEL NR32_REG -__REG NR33_REG; /** Sound Channel 3 Frequency data Low */ +__REG NR33_REG; /** Sound Channel 3 Frequency data Low */ #define rAUD3LOW NR33_REG -__REG NR34_REG; /** Sound Channel 3 Frequency data High */ +__REG NR34_REG; /** Sound Channel 3 Frequency data High */ #define rAUD3HIGH NR34_REG -__REG NR41_REG; /** Sound Channel 4 Sound Length */ +__REG NR41_REG; /** Sound Channel 4 Sound Length */ #define rAUD4LEN NR41_REG -__REG NR42_REG; /** Sound Channel 4 Volume Envelope */ +__REG NR42_REG; /** Sound Channel 4 Volume Envelope */ #define rAUD4ENV NR42_REG -__REG NR43_REG; /** Sound Channel 4 Polynomial Counter */ +__REG NR43_REG; /** Sound Channel 4 Polynomial Counter */ #define rAUD4POLY NR43_REG -__REG NR44_REG; /** Sound Channel 4 Counter / Consecutive and Inital */ +__REG NR44_REG; /** Sound Channel 4 Counter / Consecutive and Inital */ #define rAUD4GO NR44_REG -__REG NR50_REG; /** Sound Channel control / ON-OFF / Volume */ +__REG NR50_REG; /** Sound Channel control / ON-OFF / Volume */ #define rAUDVOL NR50_REG #define AUDVOL_VIN_LEFT 0b10000000u #define AUDVOL_VIN_RIGHT 0b00001000u -__REG NR51_REG; /** Sound Selection of Sound output terminal */ +__REG NR51_REG; /** Sound Selection of Sound output terminal */ #define rAUDTERM NR51_REG #define AUDTERM_4_LEFT 0b10000000u @@ -108,13 +108,15 @@ __REG NR51_REG; /** Sound Selection of Sound output terminal */ #define AUDTERM_2_RIGHT 0b00000010u #define AUDTERM_1_RIGHT 0b00000001u -__REG NR52_REG; /** Sound Master on/off */ +__REG NR52_REG; /** Sound Master on/off */ #define rAUDENA NR52_REG #define AUDENA_ON 0b10000000u #define AUDENA_OFF 0b00000000u -__REG LCDC_REG; /** LCD control */ +extern UBYTE PCM_SAMPLE[16]; /** PCM sample */ + +__REG LCDC_REG; /** LCD control */ #define rLCDC LCDC_REG #define LCDCF_OFF 0b00000000u @@ -134,7 +136,7 @@ __REG LCDC_REG; /** LCD control */ #define LCDCF_BGOFF 0b00000000u #define LCDCF_BGON 0b00000001u -__REG STAT_REG; /** LCD status */ +__REG STAT_REG; /** LCD status */ #define rSTAT STAT_REG #define STATF_LYC 0b01000000u @@ -148,44 +150,44 @@ __REG STAT_REG; /** LCD status */ #define STATF_LCD 0b00000011u #define STATF_BUSY 0b00000010u -__REG SCY_REG; /** Scroll Y */ +__REG SCY_REG; /** Scroll Y */ #define rSCY -__REG SCX_REG; /** Scroll X */ +__REG SCX_REG; /** Scroll X */ #define rSCX SCX_REG -__REG LY_REG; /** LCDC Y-coordinate */ +__REG LY_REG; /** LCDC Y-coordinate */ #define rLY LY_REG -__REG LYC_REG; /** LY compare */ +__REG LYC_REG; /** LY compare */ #define rLYC LYC_REG -__REG DMA_REG; /** DMA transfer */ +__REG DMA_REG; /** DMA transfer */ #define rDMA DMA_REG -__REG BGP_REG; /** BG palette data */ +__REG BGP_REG; /** BG palette data */ #define rBGP BGP_REG -__REG OBP0_REG; /** OBJ palette 0 data */ +__REG OBP0_REG; /** OBJ palette 0 data */ #define rOBP0 OBP0_REG -__REG OBP1_REG; /** OBJ palette 1 data */ +__REG OBP1_REG; /** OBJ palette 1 data */ #define rOBP1 OBP1_REG -__REG WY_REG; /** Window Y coordinate */ +__REG WY_REG; /** Window Y coordinate */ #define rWY WY_REG -__REG WX_REG; /** Window X coordinate */ +__REG WX_REG; /** Window X coordinate */ #define rWX WX_REG -__REG KEY1_REG; /** CPU speed */ +__REG KEY1_REG; /** CPU speed */ #define rKEY1 KEY1_REG #define rSPD KEY1_REG #define KEY1F_DBLSPEED 0b10000000u #define KEY1F_PREPARE 0b00000001u -__REG VBK_REG; /** VRAM bank */ +__REG VBK_REG; /** VRAM bank */ #define rVBK VBK_REG -__REG HDMA1_REG; /** DMA control 1 */ +__REG HDMA1_REG; /** DMA control 1 */ #define rHDMA1 HDMA1_REG -__REG HDMA2_REG; /** DMA control 2 */ +__REG HDMA2_REG; /** DMA control 2 */ #define rHDMA2 HDMA2_REG -__REG HDMA3_REG; /** DMA control 3 */ +__REG HDMA3_REG; /** DMA control 3 */ #define rHDMA3 HDMA3_REG -__REG HDMA4_REG; /** DMA control 4 */ +__REG HDMA4_REG; /** DMA control 4 */ #define rHDMA4 HDMA4_REG -__REG HDMA5_REG; /** DMA control 5 */ +__REG HDMA5_REG; /** DMA control 5 */ #define rHDMA5 HDMA5_REG #define HDMA5F_MODE_GP 0b00000000u @@ -193,7 +195,7 @@ __REG HDMA5_REG; /** DMA control 5 */ #define HDMA5F_BUSY 0b10000000u -__REG RP_REG; /** IR port */ +__REG RP_REG; /** IR port */ #define rRP RP_REG #define RPF_ENREAD 0b11000000u @@ -201,29 +203,29 @@ __REG RP_REG; /** IR port */ #define RPF_WRITE_HI 0b00000001u #define RPF_WRITE_LO 0b00000000u -__REG BCPS_REG; /** BG color palette specification */ +__REG BCPS_REG; /** BG color palette specification */ #define rBCPS BCPS_REG #define BCPSF_AUTOINC 0b10000000u -__REG BCPD_REG; /** BG color palette data */ +__REG BCPD_REG; /** BG color palette data */ #define rBCPD BCPD_REG -__REG OCPS_REG; /** OBJ color palette specification */ +__REG OCPS_REG; /** OBJ color palette specification */ #define rOCPS OCPS_REG #define OCPSF_AUTOINC 0b10000000u -__REG OCPD_REG; /** OBJ color palette data */ +__REG OCPD_REG; /** OBJ color palette data */ #define rOCPD OCPD_REG -__REG SVBK_REG; /** WRAM bank */ +__REG SVBK_REG; /** WRAM bank */ #define rSVBK SVBK_REG #define rSMBK SVBK_REG -__REG PCM12_REG; /** Sound channel 1&2 PCM amplitude (R) */ +__REG PCM12_REG; /** Sound channel 1&2 PCM amplitude (R) */ #define rPCM12 PCM12_REG -__REG PCM34_REG; /** Sound channel 3&4 PCM amplitude (R) */ +__REG PCM34_REG; /** Sound channel 3&4 PCM amplitude (R) */ #define rPCM34 PCM34_REG -__REG IE_REG; /** Interrupt enable */ +__REG IE_REG; /** Interrupt enable */ #define rIE IE_REG #define IEF_HILO 0b00010000u diff --git a/gbdk-lib/libc/gb/sfr.s b/gbdk-lib/libc/gb/sfr.s @@ -1,173 +1,87 @@ - .area _SFR (ABS) +_P1_REG = 0xFF00 ; Joystick: 1.1.P15.P14.P13.P12.P11.P10 +_SB_REG = 0xFF01 ; Serial IO data buffer +_SC_REG = 0xFF02 ; Serial IO control register +_DIV_REG = 0xFF04 ; Divider register +_TIMA_REG = 0xFF05 ; Timer counter +_TMA_REG = 0xFF06 ; Timer modulo +_TAC_REG = 0xFF07 ; Timer control +_IF_REG = 0xFF0F ; Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL +_NR10_REG = 0xFF10 ; Sound register +_NR11_REG = 0xFF11 ; Sound register +_NR12_REG = 0xFF12 ; Sound register +_NR13_REG = 0xFF13 ; Sound register +_NR14_REG = 0xFF14 ; Sound register +_NR21_REG = 0xFF16 ; Sound register +_NR22_REG = 0xFF17 ; Sound register +_NR23_REG = 0xFF18 ; Sound register +_NR24_REG = 0xFF19 ; Sound register +_NR30_REG = 0xFF1A ; Sound register +_NR31_REG = 0xFF1B ; Sound register +_NR32_REG = 0xFF1C ; Sound register +_NR33_REG = 0xFF1D ; Sound register +_NR34_REG = 0xFF1E ; Sound register +_NR41_REG = 0xFF20 ; Sound register +_NR42_REG = 0xFF21 ; Sound register +_NR43_REG = 0xFF22 ; Sound register +_NR44_REG = 0xFF23 ; Sound register +_NR50_REG = 0xFF24 ; Sound register +_NR51_REG = 0xFF25 ; Sound register +_NR52_REG = 0xFF26 ; Sound register +_PCM_SAMPLE = 0xFF30 ; PCM wave pattern +_LCDC_REG = 0xFF40 ; LCD control +_STAT_REG = 0xFF41 ; LCD status +_SCY_REG = 0xFF42 ; Scroll Y +_SCX_REG = 0xFF43 ; Scroll X +_LY_REG = 0xFF44 ; LCDC Y-coordinate +_LYC_REG = 0xFF45 ; LY compare +_DMA_REG = 0xFF46 ; DMA transfer +_BGP_REG = 0xFF47 ; BG palette data +_OBP0_REG = 0xFF48 ; OBJ palette 0 data +_OBP1_REG = 0xFF49 ; OBJ palette 1 data +_WY_REG = 0xFF4A ; Window Y coordinate +_WX_REG = 0xFF4B ; Window X coordinate +_KEY1_REG = 0xFF4D ; CPU speed +_VBK_REG = 0xFF4F ; VRAM bank +_HDMA1_REG = 0xFF51 ; DMA control 1 +_HDMA2_REG = 0xFF52 ; DMA control 2 +_HDMA3_REG = 0xFF53 ; DMA control 3 +_HDMA4_REG = 0xFF54 ; DMA control 4 +_HDMA5_REG = 0xFF55 ; DMA control 5 +_RP_REG = 0xFF56 ; IR port +_BCPS_REG = 0xFF68 ; BG color palette specification +_BCPD_REG = 0xFF69 ; BG color palette data +_OCPS_REG = 0xFF6A ; OBJ color palette specification +_OCPD_REG = 0xFF6B ; OBJ color palette data +_SVBK_REG = 0xFF70 ; WRAM bank +_PCM12_REG = 0xFF76 ; Sound channel 1&2 PCM amplitude (R) +_PCM34_REG = 0xFF77 ; Sound channel 3&4 PCM amplitude (R) +_IE_REG = 0xFFFF ; Interrupt enable - .org 0xFF00 -_P1_REG:: ; Joystick: 1.1.P15.P14.P13.P12.P11.P10 - .ds 1 - .org 0xFF01 -_SB_REG:: ; Serial IO data buffer - .ds 1 - .org 0xFF02 -_SC_REG:: ; Serial IO control register - .ds 1 - .org 0xFF04 -_DIV_REG:: ; Divider register - .ds 1 - .org 0xFF05 -_TIMA_REG:: ; Timer counter - .ds 1 - .org 0xFF06 -_TMA_REG:: ; Timer modulo - .ds 1 - .org 0xFF07 -_TAC_REG:: ; Timer control - .ds 1 - .org 0xFF0F -_IF_REG:: ; Interrupt flags: 0.0.0.JOY.SIO.TIM.LCD.VBL - .ds 1 - .org 0xFF10 -_NR10_REG:: ; Sound register - .ds 1 - .org 0xFF11 -_NR11_REG:: ; Sound register - .ds 1 - .org 0xFF12 -_NR12_REG:: ; Sound register - .ds 1 - .org 0xFF13 -_NR13_REG:: ; Sound register - .ds 1 - .org 0xFF14 -_NR14_REG:: ; Sound register - .ds 1 - .org 0xFF16 -_NR21_REG:: ; Sound register - .ds 1 - .org 0xFF17 -_NR22_REG:: ; Sound register - .ds 1 - .org 0xFF18 -_NR23_REG:: ; Sound register - .ds 1 - .org 0xFF19 -_NR24_REG:: ; Sound register - .ds 1 - .org 0xFF1A -_NR30_REG:: ; Sound register - .ds 1 - .org 0xFF1B -_NR31_REG:: ; Sound register - .ds 1 - .org 0xFF1C -_NR32_REG:: ; Sound register - .ds 1 - .org 0xFF1D -_NR33_REG:: ; Sound register - .ds 1 - .org 0xFF1E -_NR34_REG:: ; Sound register - .ds 1 - .org 0xFF20 -_NR41_REG:: ; Sound register - .ds 1 - .org 0xFF21 -_NR42_REG:: ; Sound register - .ds 1 - .org 0xFF22 -_NR43_REG:: ; Sound register - .ds 1 - .org 0xFF23 -_NR44_REG:: ; Sound register - .ds 1 - .org 0xFF24 -_NR50_REG:: ; Sound register - .ds 1 - .org 0xFF25 -_NR51_REG:: ; Sound register - .ds 1 - .org 0xFF26 -_NR52_REG:: ; Sound register - .ds 1 - .org 0xFF40 -_LCDC_REG:: ; LCD control - .ds 1 - .org 0xFF41 -_STAT_REG:: ; LCD status - .ds 1 - .org 0xFF42 -_SCY_REG:: ; Scroll Y - .ds 1 - .org 0xFF43 -_SCX_REG:: ; Scroll X - .ds 1 - .org 0xFF44 -_LY_REG:: ; LCDC Y-coordinate - .ds 1 - .org 0xFF45 -_LYC_REG:: ; LY compare - .ds 1 - .org 0xFF46 -_DMA_REG:: ; DMA transfer - .ds 1 - .org 0xFF47 -_BGP_REG:: ; BG palette data - .ds 1 - .org 0xFF48 -_OBP0_REG:: ; OBJ palette 0 data - .ds 1 - .org 0xFF49 -_OBP1_REG:: ; OBJ palette 1 data - .ds 1 - .org 0xFF4A -_WY_REG:: ; Window Y coordinate - .ds 1 - .org 0xFF4B -_WX_REG:: ; Window X coordinate - .ds 1 - .org 0xFF4D -_KEY1_REG:: ; CPU speed - .ds 1 - .org 0xFF4F -_VBK_REG:: ; VRAM bank - .ds 1 - .org 0xFF51 -_HDMA1_REG:: ; DMA control 1 - .ds 1 - .org 0xFF52 -_HDMA2_REG:: ; DMA control 2 - .ds 1 - .org 0xFF53 -_HDMA3_REG:: ; DMA control 3 - .ds 1 - .org 0xFF54 -_HDMA4_REG:: ; DMA control 4 - .ds 1 - .org 0xFF55 -_HDMA5_REG:: ; DMA control 5 - .ds 1 - .org 0xFF56 -_RP_REG:: ; IR port - .ds 1 - .org 0xFF68 -_BCPS_REG:: ; BG color palette specification - .ds 1 - .org 0xFF69 -_BCPD_REG:: ; BG color palette data - .ds 1 - .org 0xFF6A -_OCPS_REG:: ; OBJ color palette specification - .ds 1 - .org 0xFF6B -_OCPD_REG:: ; OBJ color palette data - .ds 1 - .org 0xFF70 -_SVBK_REG:: ; WRAM bank - .ds 1 - .org 0xFF76 -_PCM12_REG:: ; Sound channel 1&2 PCM amplitude (R) - .ds 1 - .org 0xFF77 -_PCM34_REG:: ; Sound channel 3&4 PCM amplitude (R) - .ds 1 - .org 0xFFFF -_IE_REG:: ; Interrupt enable - .ds 1 - +.globl _P1_REG +.globl _SB_REG, _SC_REG +.globl _DIV_REG +.globl _TIMA_REG, _TMA_REG, _TAC_REG +.globl _IF_REG +.globl _NR10_REG, _NR11_REG, _NR12_REG, _NR13_REG, _NR14_REG +.globl _NR21_REG, _NR22_REG, _NR23_REG, _NR24_REG +.globl _NR30_REG, _NR31_REG, _NR32_REG, _NR33_REG, _NR34_REG +.globl _NR41_REG, _NR42_REG, _NR43_REG, _NR44_REG +.globl _NR50_REG, _NR51_REG, _NR52_REG +.globl _PCM_SAMPLE +.globl _LCDC_REG +.globl _STAT_REG +.globl _SCY_REG, _SCX_REG +.globl _LY_REG, _LYC_REG +.globl _DMA_REG +.globl _BGP_REG +.globl _OBP0_REG, _OBP1_REG +.globl _WY_REG, _WX_REG +.globl _KEY1_REG +.globl _VBK_REG +.globl _HDMA1_REG, _HDMA2_REG, _HDMA3_REG, _HDMA4_REG, _HDMA5_REG +.globl _RP_REG +.globl _BCPS_REG, _BCPD_REG +.globl _OCPS_REG, _OCPD_REG +.globl _SVBK_REG +.globl _PCM12_REG, _PCM34_REG +.globl _IE_REG +
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